摘要
本设计用可编程逻辑器件(FPGA)实现了一种低密度奇偶校验 LDPC(Low Density Parity Check)码。本文所提到的 LDPC 码是采用并行编码和部分并行译码结构。同时本文采用的是一种系统码结构,这种码的最主要的优点就是它的生成矩阵能够很容易地从奇偶校验矩阵的一定变换而得到,这样,应用 FPGA 实现译码器的同时,能够简单有效地实现对应的编码器。该设计是针对分组块长为345比特,码率为4/5,采用了6位量化方案。本文用现场可编程门降列(FPGA)实现了 LDPC 码的编码,译码电路,并且通过 QUARTUS 仿真测试以及下载到实验板 ATERA 芯片的调试,表现出好的纠错性能。
We have implemented a class of Low Density Parity Check(LDPC)codes with FPGA technique.The codes considered here are based on parallelly concatenated parity check encoding and partly parallelly decoding structure.We have used the system code,and a major advantage of these codes is that the generator matrix can be got from the pari- ty check matrix easily,which leads to efficient FPGA implementations for the encoder and the decoder.Our designs use 6-bit quantizaton with a code rate of 4/5 and a block size of 345 bits.We have applied FPGA technique to imple- ment LDPC encoding and decoding circuit and performed QUARTUS simulation test,then downloaded it to break- board construction with ATERA chip for hardware debugging,which has shown a good error-correct performance.
出处
《计算机科学》
CSCD
北大核心
2004年第8期197-200,共4页
Computer Science
