摘要
在芯片设计中会经常使用到ROM,而ROM又经常作为片外存储器被所设计的芯片进行读写操作,在这里就需要设计接口电路用来配合ROM和设计的芯片。ROM多为异步工作方式,如果设计的电路为同步电路,之间又存在着接口时序配合的问题。文中介绍一种基于状态机的ROM接口电路模型。该模型有两个特点:一是采用状态机实现同步时序电路与ROM异步时序电路的接口时序配合;二是实现与具有不同时间参数ROM接口电路的兼容。该模型的设计结果通过了FPGA验证,并在ASIC芯片中得到运用。
ROM is a cell used frequently in IC design, while ROM is often operated by the IC designed as an outer memory. Here an interface circuit must be designed to cooperate the ROM and the IC designed. ROM is often used as asynchronous circuit. If the circuit you designed works as synchronous circuit, you need to match the timing between them. The paper introduces an interface model based on finite state machine, which is used for ROM. There are two properities for the model: 1) Finite state machine is used to implement interface for asynchronous ROM circuit; 2) It is compatible to universal ROM interface with different parameters. The design has been implemented into IC, which is verified by FPGA and applied in ASIC.
出处
《微机发展》
2004年第10期85-87,共3页
Microcomputer Development
关键词
状态机
同步
异步
兼容
FSM
synchronous
asynchronous
compatible
