摘要
提出了一种采用软硬件协同工作的方式来实现MIPSCPUCORE的可测性设计(DFT)方案。硬件全兼容IEEE1149.1(JTAG)标准,支持单步、断点(6个),内部关键寄存器的查看,并具有可扩充性;软件采用GUI编程开发,达到可视化DEBUG。本设计对于减少CPU开发的测试成本,提高开发效率,以及CPU测试DFT策略的经验积累,都有着一定的意义。
This article presents a DFT(design-for-test) solution which uses hardware & software cooperation to realize MIPS CPU CORE DFT. The hardware is fully compatible with IEEE1149.1 (JTAG), supporting breakpoint, step, internal key register watch function and can be extended. Software uses GUI programming to achieve visual DEBUG. The design in this paper is meaningful for reducing the test costs for CPU design, increasing design efficiency and accumulating experience of DFT strategy for CPU test. It assumes reader familiarity with IEEE1149.1.
出处
《微电子学与计算机》
CSCD
北大核心
2004年第7期6-9,共4页
Microelectronics & Computer
基金
863计划SOC项目组资助(2002AA1Z1060)
