摘要
为实现24bit音频DAC的数字前端低功耗、微面积的设计,提出了一种新的面积优化方法.优化了有限冲击响应(FIR)插值滤波器结构,同时采用改进的非递归公共子式消除算法和加法器、寄存器共用的方法来减小硬件开销和面积.优化的4阶3bit Sigma-Delta调制器克服了单比特量化器需随机加抖的问题和减轻了对后续模拟重建滤波器的性能要求.该数字部分采SMIC 40nm 1P6M标准CMOS工艺设计,核心芯片面积为0.058mm2,在1.1V电源电压仿真下,得到功耗为53μW,峰值信噪比(SNR)达到了146dB,谐波失真(THD)为-150dB,实现了高性能低功耗的要求.
One area-efficient technique is applied to accomplish digital front-end of 24-bit audio digital-to-analog converter(DAC)with low power consumption and less area.For reducing hardware overhead and area,finiteimpulse response(FIR)filter is implemented with optimized structure,improved non-recursive common subexpression elimination,adders and registers reusability.Optimal 4th order 3bit sigma delta modulator overcomes the need of dither and relaxes the requirement of analog post filtering.The digital part is implemented in SMIC 40nm1P6 Mprocess,the total core area is 0.058mm2.From the simulation of this digital part with the power supply of 1.1V,the power consumption is 53μW.At the same time,the peak signal to noise(SNR)achieves 146dB,and THD is-150dB.
出处
《微电子学与计算机》
CSCD
北大核心
2015年第5期36-40,共5页
Microelectronics & Computer
