摘要
VHDL是EDA的重要组成部分,利用VHDL来设计数字频率计,极大地减少了设计电路的时间和可能发生的错误,降低开发成本。本文介绍了数字频率计的工作原理,应用VHDL设计的顶层文件及其运行结果。
VHDL is one of the most important components of EDA. Designing digital frequency indicator with PHDL can not only save time for designing electrocircuit, but also decrease possible errors. Moreover, it can reduce the cost of electrocircuit design. This article introduces the principle of digital frequency indicator and presents VHDL top file and the results of its application.
关键词
数字频率计
VHDL
设计
digital frequency indicator VHDL design
