摘要
Thin p + layers with good electrical properties were fabricated by RTA (rapid thermal annealing) with post FA (furance annealing) of Si +/B + dual implanted silicon wafers. The electrical and structural characteristics of thin p + layers have been measured by FPP (four point probe), SRP (spreading resistance probe), RBS/channelling. Optimizing the implantation and annealing processes, especially using the thermal cycle of RTA followed by FA, shallow p +n junctions can be fabricated, which shows excellent I V characteristics with revers bias leakage current densities of 1.8?nA/cm 2 at -1.4?V.
Thin p(+) layers with good electrical properties were fabricated by RTA (rapid thermal annealing) with post-FA (furance annealing) of Si+/B+ dual implanted silicon wafers. The electrical and structural characteristics of thin p(+) layers have been measured by FPP (four-point probe), SRP (spreading resistance probe), RBS/channelling. Optimizing the implantation and annealing processes, especially using the thermal cycle of RTA followed by FA, shallow p(+) n junctions can be fabricated, which shows excellent IN characteristics with revers-bias leakage current densities of 1.8 nA/cm(2) at -1.4 V.
出处
《中国有色金属学会会刊：英文版》
CSCD
2001年第5期753-755,共3页
Transactions of Nonferrous Metals Society of China
基金
Project( 6 99710 0 7)supportedbytheNationalNaturalScienceFoundationofChina
ProjectsupportedbyHuoYinDongFoun dation
ProjectsupportedbyEYTPofMinistryofEducation
P .R .China
