摘要
介绍了一种10M/100M以太网控制器的实现方法,该控制器以FIFO作为帧缓存,通过程序设计实现10M/100M自适应,设计中采用WS接口,提高了设计的灵活行,可以实现与其他SOC的互连[1],该设计采用VerilogHDL硬件描述语言编程,基于ISE开发环境,在Xilinx公司的Spartan-Ⅲ系列FPGA XC3S1000-4-FT256C上实现。
Introduced the design of 10M/100M Ethernet controller base on FPGA Adopt two fifo as data buffer,to realize 10M/100M adapt through program design.using WS interface,to improve the flexible of the design.can also use the WS interface to implement interlinkage between different design with WS interface.Using VerilogHDL language to implement the design,base on ISE environment,adopts the XC3S1000-ft256-4-C of Xilinx company as kernel device.
出处
《太原理工大学学报》
CAS
北大核心
2008年第S1期27-29,共3页
Journal of Taiyuan University of Technology
基金
国家自然科学基金(60372058
60772101)
山西省自然科学基金(20051009)
