摘要
在BIST测试过程中,测试电路的加入使得数字系统的功耗明显加大,低功耗的BIST设计得到人们的广泛关注。本文介绍几种BIST的低功耗设计技术,各种方法的综合应用会使系统的功耗指标达到最佳。
During the BIST testing, power consumption of digital system may increase significantly due to the
test circuits. The power of a digital system is considerably higher in test mode than in system mode. In this pa-
per, we present several novel low power BIST design techniques. The integration of several methods utilizing the
advantage and remedying the disadvantage will make tbe low power design of system to optimum.
出处
《仪器仪表学报》
EI
CAS
CSCD
北大核心
2003年第z2期629-630,632,共3页
Chinese Journal of Scientific Instrument
