摘要
叙述了全数字锁相环的工作原理,提出了应用VHDL技术设计全数字锁相环的方法,并用复杂可编程逻辑器件CPLD予以实现,给出了系统主要模块的设计过程和仿真结果。
In this paper,the operation principle of digital phase locked loop(DPLL) is introduced.A method for designing DPLL is proposed based on VHDL technique,and realized with complex programmable logic device(CPLD).The designing processes and the simulating results of the main modules are given.
出处
《长春工程学院学报（自然科学版）》
2005年第3期53-56,共4页
Journal of Changchun Institute of Technology：Natural Sciences Edition
