摘要
本文介绍采用深亚微米CMOS工艺设计的全差分采样/保持电路,该电路应用下极板采样技术和全差分结构以消除开关电荷注入和时钟馈通引起的误差,从而获得高精度。设计采用0.18μm CMOS工艺条件并通过spectre软件模拟仿真,结果表明电路在3 V电源电压和50MHz采样频率工作条件下能够稳定工作。
A deep sub-micron full differential sample/hold circuit is presented.The circuit adopts deep sub-micron technology to increase the speed.The design employs the bottom plate sampling technique and full differential structure,which eliminate the charge-injection error and clock feed-through effect with an improved accuracy.The circuit has been simulated in 0.18μm CMOS process by Spectre at 3 V supply.The result of simulation shows the circuit can work correctly at 50MHz sampling frequency.
出处
《仪器仪表学报》
EI
CAS
CSCD
北大核心
2006年第z1期145-147,共3页
Chinese Journal of Scientific Instrument
关键词
CMOS深亚微米
全差分
下极板采样
CMOS deep sub-micron full differential bottom plate sampling
