摘要
该文设计实现了一个四阶的跳耦Delta-Sigma DAC。基于过采样技术和反馈控制技术,Delta-Sigma调制器在高精度数据转换器实现方面比其他方案有更多优势。这种拓扑结构对于系数的变化不敏感。为了以最优的方式实现调制器,给出了最小字长Delta-Sigma调制器的设计方法。调制器系数量化成了2的幂次,因此系数乘法可以通过移位操作实现,而同时调制器性能并未因此而下降。信噪比并未因为字长的减小而变化。
This paper describes the design of a 4th-order leapfrog [1] delta-sigma DAC.This topology is less sensitive to coefficient variation.In order to implement the modulator in a most efficient way,here also gives a method of minimizing the word-length of delta-sigma modulator.Further coefficients of the modulator are quantized to power-of-two,so multiplication operations are simplified to bit-shift operations.At the same time the performance is not reduced.Signal to noise ratio(SNR) is the criterion for word-length reduction.
出处
《杭州电子科技大学学报（自然科学版）》
2007年第5期39-42,共4页
Journal of Hangzhou Dianzi University：Natural Sciences
