摘要
相较于单个硅绝缘栅双极型晶体管(Si IGBT)芯片,碳化硅(SiC)芯片的载流量较小,因此对于同功率等级的功率模块,需要并联更多的芯片。然而,芯片数量的增多会增大模块失效的风险,因此需要一种低寄生电感低结温的封装设计,来提高多芯片并联SiC模块的可靠性。这里通过对多芯片布局以及垫片位置分布的研究,设计出一款低寄生电感,低结温的多芯片并联功率模块结构。最终基于实验和多物理场仿真软件COMSOL对该封装结构进行验证,实验及仿真结果表明所设计的多芯片并联SiC模块满足低感、低结温的设计目标。
The silicon carbide(SiC)chip has a smaller flux than a single silicon insulated gate bipolar transistor(Si IGBT)chip,thus more and more chips need to be connected in parallel for a power module of the same power class.However,increasing the number of chips will increase the risk of module failure,so a package design with low parasitic inductance and low junction temperature is needed to improve the reliability of multi-chip parallel SiC.By explore the layout of multi-chip and the position of support,a low parasitic inductance and low junction temperature multi-chip parallel power module structure is designed.Finally,the package structure is verified by experiment and multi-physical field simulation software COMSOL.Experiment and simulation results show that the designed multi-chip parallel SiC module meets the design objectives of low parasitic inductance and low junction temperature.
作者
王佳宁
黄耀东
周伟男
吴馥晨
WANG Jia-ning;HUANG Yao-dong;ZHOU Wei-nan;WU Fu-chen(Hefei University of Technology,Hefei 230009,China)
出处
《电力电子技术》
北大核心
2023年第9期133-135,140,共4页
Power Electronics
关键词
功率模块
封装设计
多芯片并联
power module
package design
multi-chip parallel
