摘要
电容(储存单元)是DRAM(动态随机存取存储器)非常关键的结构。由于高深宽比电容孔刻蚀的限制,随着器件尺寸越来越小,同时实现足够的电容值、最小化存储单元之间的漏电和最大化存储阵列密度变得越来越具有挑战性。为了构建小尺寸和笔直剖面的电容孔,我们在此基于在中微CCP干法刻蚀机上的实验结果提供了一些工艺解决方案,例如激发等离子体的射频功率、刻蚀化学气体和逐步刻蚀调整等。这些解决方案主要针对工艺挑战包括工艺剖面不弯曲、大的底部尺寸和良好的底部圆度等。而且,我们根据经验和相关知识提出了相应的机理,涉及但不限于电容耦合式等离子体刻蚀过程中的聚合物沉积、离子轰击和化学反应等。
Capacitor i.e.storage node is the critical role in dynamic random access memory device.With the smaller size,achieving enough capacitance storage value,minimized capacitor-to-capacitor leakage and maximized capacitor density become more and more challenging,due to the limitation of high-aspect-ratio capacitor etch.To fabricate a capacitor hole with very small critical dimension and straight profile,we here provide some process solutions,such as tuning power and chemistry,step by step,on a capacitive coupled plasma etch tool,based on our experimental results.The challenges,we here addressed,include bowing-free profile,large bottom critical dimension and better circularity at bottom.We also try to explain the mechanism of them according to the experience and the knowledge of polymer deposition,ion bombardment and chemical reaction in capacitive coupled plasma etch.
作者
侯剑秋
于新新
孙玉乐
周娅
李振兴
鲍锡飞
张泳富
胡增文
HOU Jianqiu;YU Xinxin;SUNYule;ZHOUYa;LI Zhenxing;BAO Xifei;CHANG Jerome;HU Zengwen(Advanced Micro-Fabrication Equipment Inc.China,Shanghai 201201,China;Chang Xin Memory Technologies Corporation,Hefei 230093,China)
出处
《微纳电子与智能制造》
2021年第4期92-102,共11页
Micro/nano Electronics and Intelligent Manufacturing
