As the front-end preamplifiers in optical receivers, transimpedance amplifiers （TIAs） are commonly required to have a high gain and low input noise to amplify the weak and susceptible input signal. At the same time,...As the front-end preamplifiers in optical receivers, transimpedance amplifiers （TIAs） are commonly required to have a high gain and low input noise to amplify the weak and susceptible input signal. At the same time, the TIAs should possess a wide dynamic range （DR） to prevent the circuit from becoming saturated by high input currents. Based on the above, this paper presents a CMOS transimpedance amplifier with high gain and a wide DR for 2.5 Gbit/s communications. The TIA proposed consists of a three-stage cascade pull push inverter, an automatic gain control circuit, and a shunt transistor controlled by the resistive divider. The inductive-series peaking technique is used to further extend the bandwidth. The TIA proposed displays a maximum transimpedance gain of 88.3 dBΩ with the -3 dB bandwidth of 1.8 GHz, exhibits an input current dynamic range from 100 nA to 10 mA. The output voltage noise is less than 48.23 nV/√Hz within the -3 dB bandwidth. The circuit is fabricated using an SMIC 0.18 μm 1P6M RFCMOS process and dissipates a dc power of 9.4 mW with 1.8 V supply voltage.展开更多
For time-of-flight(TOF)light detection and ranging(LiDAR),a three-channel high-performance transimpedance amplifier(TIA)with high immunity to input load capacitance is presented.A regulated cascade(RGC)as the input st...For time-of-flight(TOF)light detection and ranging(LiDAR),a three-channel high-performance transimpedance amplifier(TIA)with high immunity to input load capacitance is presented.A regulated cascade(RGC)as the input stage is at the core of the complementary metal oxide semiconductor(CMOS)circuit chip,giving it more immunity to input photodiode detectors.A simple smart output interface acting as a feedback structure,which is rarely found in other designs,reduces the chip size and power consumption simultaneously.The circuit is designed using a 0.5μm CMOS process technology to achieve low cost.The device delivers a 33.87 dB?transimpedance gain at 350 MHz.With a higher input load capacitance,it shows a-3 dB bandwidth of 461 MHz,indicating a better detector tolerance at the front end of the system.Under a 3.3 V supply voltage,the device consumes 5.2 mW,and the total chip area with three channels is 402.8×597.0μm2(including the test pads).展开更多
A fully integrated 40 Gbit/s optical receiver analog front-end （AFE） including a transimpedance amplifier （TIA） and a limiting amplifier （LA） for short distance communication is described in this paper. The prop...A fully integrated 40 Gbit/s optical receiver analog front-end （AFE） including a transimpedance amplifier （TIA） and a limiting amplifier （LA） for short distance communication is described in this paper. The proposed TIA employs a modified regulated cascode （RGC） configuration as input stage, and adopts a third order interleaving active feedback gain stage. The LA utilizes nested active feedback, negative capacitance, and inductor peaking technology to achieve high voltage gain and wide bandwidth. The tiny photo current received by the receiver AFE is amplified to a single-ended voltage swing of 200 mV（p-p）. Simulation results show that the receiver AFE provides conversion gain of up to 83 dBΩ and bandwidth of 34.7 GHz, and the equivalent input noise current integrated from 1 MHz to 30 GHz is about 6.6 μA（rms）.展开更多
A differential cross-coupled regulated cascode(RGC)transimpedance amplifier(TIA)is proposed. The theory of multi-stage common-source(CS) configuration as an auxiliary amplifier to enhance the bandwidth and output impe...A differential cross-coupled regulated cascode(RGC)transimpedance amplifier(TIA)is proposed. The theory of multi-stage common-source(CS) configuration as an auxiliary amplifier to enhance the bandwidth and output impedance of RGC topology is analyzed. Additionally, negative Miller capacitance and shunt active inductor compensation are exploited to further expand the bandwidth. The proposed RGC TIA is simulated based on UMC 0.18 μm standard CMOS process. The simulation results demonstrate that the proposed TIA has a high transimpedance of 60.5 d B?, and a-3 d B bandwidth of 5.4 GHz is achieved for 0.5 p F input capacitance. The average equivalent input noise current spectral density is about 20 p A/Hz^(1/2) in the interested frequency, and the TIA consumes 20 m W DC power under 1.8 V supply voltage. The voltage swing is 460 m V pp, and the saturation input current is 500 μA.展开更多
This study presents a CMOS receiver chip realized in 0.18μm standard CMOS technology and in- tended for high precision 3-D laser radar. The chip includes an adjustable gain transimpedance pre-amplifier, a post-amplif...This study presents a CMOS receiver chip realized in 0.18μm standard CMOS technology and in- tended for high precision 3-D laser radar. The chip includes an adjustable gain transimpedance pre-amplifier, a post-amplifier and two timing comparators. An additional feedback is employed in the regulated cascode tran- simpedance amplifier to decrease the input impedance, and a variable gain transimpedance amplifier controlled by digital switches and analog multiplexer is utilized to realize four gain modes, extending the input dynamic range. The measurement shows that the highest transimpedance of the channel is 50 kΩ, the uncompensated walk error is 1.44 ns in a wide linear dynamic range of 66 dB （1 ： 2000）, and the input referred noise current is 2.3 pA/√ （rms）, resulting in a very low detectable input current of 1μA with SNR = 5.展开更多
A zero-pole cancellation transimpedance amplifier（TIA）has been realized in 0.35μm RF CMOS technology for Gigabit Ethernet applications.The TIA exploits a zero-pole cancellation configuration to isolate the input pa...A zero-pole cancellation transimpedance amplifier（TIA）has been realized in 0.35μm RF CMOS technology for Gigabit Ethernet applications.The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration.Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ωfor 1.5 pF photodiode capaci- tance,with a gain-bandwidth product of 3.4 THz·Ω.Even with 2 pF photodiode capacitance,the bandwidth exhibits a decline of only 300 MHz,confirming the mechanism of the zero-pole cancellation configuration.The input resis- tance is 50Ω,and the average input noise current spectral density is 9.7 pA/√ Hz.Testing results shows that the eye diagram at 1 Gb/s is wide open.The chip dissipates 17 mW under a single 3.3 V supply.展开更多
This work presents a high-gain broadband inverter-based cascode transimpedance amplifier fabricated in a 65-nm CMOS process.Multiple bandwidth enhancement techniques,including input bonding wire,input series on-chip i...This work presents a high-gain broadband inverter-based cascode transimpedance amplifier fabricated in a 65-nm CMOS process.Multiple bandwidth enhancement techniques,including input bonding wire,input series on-chip inductive peak-ing and negative capacitance compensation,are adopted to overcome the large off-chip photodiode capacitive loading and the miller capacitance of the input device,achieving an overall bandwidth enhancement ratio of 8.5.The electrical measure-ment shows TIA achieves 58 dBΩup to 12.7 GHz with a 180-fF off-chip photodetector.The optical measurement demonstrates a clear open eye of 20 Gb/s.The TIA dissipates 4 mW from a 1.2-V supply voltage.展开更多
This study presents a hybrid algorithm obtained by combining a genetic algorithm (GA) with successive quadratic sequential programming (SQP), namely GA-SQP. GA is the main optimizer, whereas SQP is used to refine the ...This study presents a hybrid algorithm obtained by combining a genetic algorithm (GA) with successive quadratic sequential programming (SQP), namely GA-SQP. GA is the main optimizer, whereas SQP is used to refine the results of GA, further improving the solution quality. The problem formulation is done in the framework named RUNE (fRamework for aUtomated aNalog dEsign), which targets solving nonlinear mono-objective and multi-objective optimization problems for analog circuits design. Two circuits are presented: a transimpedance amplifier (TIA) and an optical driver (Driver), which are both part of an Optical Network-on-Chip (ONoC). Furthermore, convergence characteristics and robustness of the proposed method have been explored through comparison with results obtained with SQP algorithm. The outcome is very encouraging and suggests that the hybrid proposed method is very efficient in solving analog design problems.展开更多
The design and measurement of a snap-shot mode cryogenic readout circuit（ROIC） for GaAs/AlGaAs QWIP FPAs was reported.CTIA input circuits with pixei level built-in electronic injection transistors were proposed to t...The design and measurement of a snap-shot mode cryogenic readout circuit（ROIC） for GaAs/AlGaAs QWIP FPAs was reported.CTIA input circuits with pixei level built-in electronic injection transistors were proposed to test the chip before assembly with a detector array.Design optimization techniques for cryogenic and low power are analyzed.An experimental ROIC chip of a 128×128 array was fabricated in 0.35μm CMOS technology.Measurements showed that the ROIC could operate at 77 K with low power dissipation of 35 mW.The chip has a pixel charge capacity of 2.57×10^6 electrons and transimpedance of 1.4×10^7Ω.Measurements showed that the transimpedance non-uniformity was less than 5%with a 10 MHz readout speed and a 3.3 V supply voltage.展开更多
There are certain limitations in the application of uncooled focal plane array （FPA） detector due to the lack of an effective response model which reliably transforms the target temperature to analog output voltage....There are certain limitations in the application of uncooled focal plane array （FPA） detector due to the lack of an effective response model which reliably transforms the target temperature to analog output voltage. This paper establishes the response model of microbolometer through researching the detection theory of microbolometer and the heat balance equation under the condition of the pulsed voltage bias. In the establishing process, we simplified the heat balance equation to acquire a simple answer. The experimental data show that, in the temperature dynamic range of 30 K, the biggest tolerance between the model data and the experiment data is 0.2 K; while in the temperature dynamic range of 100 K, it is 1 K. This model can reflect the real response of the microbolometer with only small differences which are acceptable in engineering applications.展开更多
This paper presents a 26-Gb/s CMOS optical receiver that is fabricated in 65-nm technology. It consists of a tripleinductive transimpedance amplifier(TIA), direct current(DC) offset cancellation circuits, 3-stage gm-T...This paper presents a 26-Gb/s CMOS optical receiver that is fabricated in 65-nm technology. It consists of a tripleinductive transimpedance amplifier(TIA), direct current(DC) offset cancellation circuits, 3-stage gm-TIA variable-gain amplifiers(VGA), and a reference-less clock and data recovery(CDR) circuit with built-in equalization technique. The TIA/VGA frontend measurement results demonstrate 72-dB? transimpedance gain, 20.4-GHz-3-dB bandwidth, and 12-dB DC gain tuning range. The measurements of the VGA’s resistive networks also demonstrate its efficient capability of overcoming the voltage and temperature variations. The CDR adopts a full-rate topology with 12-dB imbedded equalization tuning range. Optical measurements of this chipset achieve a 10-12 BER at 26 Gb/s for a 2;-1 PRBS input with a-7.3-dBm input sensitivity. The measurement results with a 10-dB @ 13 GHz attenuator also demonstrate the effectiveness of the gain tuning capability and the built-in equalization. The entire system consumes 140 mW from a 1/1.2-V supply.展开更多
A 12-Gbit/s low-power,wide-bandwidh CMOS(complementary metal oxide semiconductor)dual negative feedback feed-forward common gate(DNFFCG)differential trans-impedance amplifier(TIA)is presented for the veryshort-reach(V...A 12-Gbit/s low-power,wide-bandwidh CMOS(complementary metal oxide semiconductor)dual negative feedback feed-forward common gate(DNFFCG)differential trans-impedance amplifier(TIA)is presented for the veryshort-reach(VSR)optoelectronic integrated circuit(OEIC)receiver.The dominant pole of the input node is shifted up to a high frequency,and thus the bandwidth of the CMOS DNFFCG TIA is improved.Besides,two negative feedback loops are used to reduce the input impedance and further increase the bandwidth.The proposed TIA was fabricated using TSMC 0.18 jxm CMOS technology.The whole circuit has a compact chip area,the core area of which is only 0.003 6 mm2.The power consumption is 14.6 mW excluding 2-stage differential buffers.The test results indicate that the 3 dB bandwidth of 9 GHz is achieved with a 1 8 V supply voltage and its trans-impedance gain is 49.2 dBH.The measured average equivalent input noise current density is 28.1 pA H z12.Under the same process conditions,the DNFFCG has better gain bandwidth product compared with those in the published papers.展开更多
A 10 Gbit/s burst-mode preamplifier is designed for passive optical networks （PONs）. To achieve a high dynamic range and fast response, the circuit is DC coupled, and a feed-back type peak detector is designed to pe...A 10 Gbit/s burst-mode preamplifier is designed for passive optical networks （PONs）. To achieve a high dynamic range and fast response, the circuit is DC coupled, and a feed-back type peak detector is designed to perform auto-gaincontrol and threshold extraction. Regulated cascade （RGC） architecture is exploited as the input stage to reduce the input impedance of the circuit and isolate the large parasitic capacitance including the photodiode capacitance from the determination pole, thus increasing the bandwidth. This preamplifier is implemented using the low-cost 0. 13 ixm CMOS technology. The die area is 425 μm × 475 μm and the total power dissipation is 23.4 mW. The test results indicate that the preamplifier can work at a speed from 1.25 to 10.312 5 Gbit/s, providing a high transimpedance gain of 64.0 dBΩ and a low gain of 54. 6 dBl2 with a dynamic input range of over 22.9 dB. The equivalent input noise current is 23. 4 pA/ Hz1/2. The proposed burst amplifier satisfies related specifications defined in 10G-EPON and XG-PON standards.展开更多
基金supported by the National Natural Science Foundation of China(Nos.61376033,61006028)the National High-Tech Program of China(Nos.2012AA012302,2013AA014103)the Opening Project of Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory
文摘As the front-end preamplifiers in optical receivers, transimpedance amplifiers （TIAs） are commonly required to have a high gain and low input noise to amplify the weak and susceptible input signal. At the same time, the TIAs should possess a wide dynamic range （DR） to prevent the circuit from becoming saturated by high input currents. Based on the above, this paper presents a CMOS transimpedance amplifier with high gain and a wide DR for 2.5 Gbit/s communications. The TIA proposed consists of a three-stage cascade pull push inverter, an automatic gain control circuit, and a shunt transistor controlled by the resistive divider. The inductive-series peaking technique is used to further extend the bandwidth. The TIA proposed displays a maximum transimpedance gain of 88.3 dBΩ with the -3 dB bandwidth of 1.8 GHz, exhibits an input current dynamic range from 100 nA to 10 mA. The output voltage noise is less than 48.23 nV/√Hz within the -3 dB bandwidth. The circuit is fabricated using an SMIC 0.18 μm 1P6M RFCMOS process and dissipates a dc power of 9.4 mW with 1.8 V supply voltage.
文摘For time-of-flight(TOF)light detection and ranging(LiDAR),a three-channel high-performance transimpedance amplifier(TIA)with high immunity to input load capacitance is presented.A regulated cascade(RGC)as the input stage is at the core of the complementary metal oxide semiconductor(CMOS)circuit chip,giving it more immunity to input photodiode detectors.A simple smart output interface acting as a feedback structure,which is rarely found in other designs,reduces the chip size and power consumption simultaneously.The circuit is designed using a 0.5μm CMOS process technology to achieve low cost.The device delivers a 33.87 dB?transimpedance gain at 350 MHz.With a higher input load capacitance,it shows a-3 dB bandwidth of 461 MHz,indicating a better detector tolerance at the front end of the system.Under a 3.3 V supply voltage,the device consumes 5.2 mW,and the total chip area with three channels is 402.8×597.0μm2(including the test pads).
基金supported by the National Natural Science Foundation of China (60976029)
文摘A fully integrated 40 Gbit/s optical receiver analog front-end （AFE） including a transimpedance amplifier （TIA） and a limiting amplifier （LA） for short distance communication is described in this paper. The proposed TIA employs a modified regulated cascode （RGC） configuration as input stage, and adopts a third order interleaving active feedback gain stage. The LA utilizes nested active feedback, negative capacitance, and inductor peaking technology to achieve high voltage gain and wide bandwidth. The tiny photo current received by the receiver AFE is amplified to a single-ended voltage swing of 200 mV（p-p）. Simulation results show that the receiver AFE provides conversion gain of up to 83 dBΩ and bandwidth of 34.7 GHz, and the equivalent input noise current integrated from 1 MHz to 30 GHz is about 6.6 μA（rms）.
基金Supported by the National Natural Science Foundation of China(No.61474081)
文摘A differential cross-coupled regulated cascode(RGC)transimpedance amplifier(TIA)is proposed. The theory of multi-stage common-source(CS) configuration as an auxiliary amplifier to enhance the bandwidth and output impedance of RGC topology is analyzed. Additionally, negative Miller capacitance and shunt active inductor compensation are exploited to further expand the bandwidth. The proposed RGC TIA is simulated based on UMC 0.18 μm standard CMOS process. The simulation results demonstrate that the proposed TIA has a high transimpedance of 60.5 d B?, and a-3 d B bandwidth of 5.4 GHz is achieved for 0.5 p F input capacitance. The average equivalent input noise current spectral density is about 20 p A/Hz^(1/2) in the interested frequency, and the TIA consumes 20 m W DC power under 1.8 V supply voltage. The voltage swing is 460 m V pp, and the saturation input current is 500 μA.
文摘This study presents a CMOS receiver chip realized in 0.18μm standard CMOS technology and in- tended for high precision 3-D laser radar. The chip includes an adjustable gain transimpedance pre-amplifier, a post-amplifier and two timing comparators. An additional feedback is employed in the regulated cascode tran- simpedance amplifier to decrease the input impedance, and a variable gain transimpedance amplifier controlled by digital switches and analog multiplexer is utilized to realize four gain modes, extending the input dynamic range. The measurement shows that the highest transimpedance of the channel is 50 kΩ, the uncompensated walk error is 1.44 ns in a wide linear dynamic range of 66 dB （1 ： 2000）, and the input referred noise current is 2.3 pA/√ （rms）, resulting in a very low detectable input current of 1μA with SNR = 5.
基金supported by the National Natural Science Foundation of China(Nos.60536030,60502005)the National High Technology Research and Development Program of China(Nos.2007AA01Z2A5,2006AA01Z239,2007AA03Z454)
文摘A zero-pole cancellation transimpedance amplifier（TIA）has been realized in 0.35μm RF CMOS technology for Gigabit Ethernet applications.The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration.Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ωfor 1.5 pF photodiode capaci- tance,with a gain-bandwidth product of 3.4 THz·Ω.Even with 2 pF photodiode capacitance,the bandwidth exhibits a decline of only 300 MHz,confirming the mechanism of the zero-pole cancellation configuration.The input resis- tance is 50Ω,and the average input noise current spectral density is 9.7 pA/√ Hz.Testing results shows that the eye diagram at 1 Gb/s is wide open.The chip dissipates 17 mW under a single 3.3 V supply.
基金supported in part by the National NaturalScience Foundation of China under Grant 62074074in part by Natural Science Foundation of Guangdong Province under Grant 2021A1515011266in part by the Science and Technology Plan of Shenzhen under Grants JCYJ20190809142017428 and JCYJ20200109141225025。
文摘This work presents a high-gain broadband inverter-based cascode transimpedance amplifier fabricated in a 65-nm CMOS process.Multiple bandwidth enhancement techniques,including input bonding wire,input series on-chip inductive peak-ing and negative capacitance compensation,are adopted to overcome the large off-chip photodiode capacitive loading and the miller capacitance of the input device,achieving an overall bandwidth enhancement ratio of 8.5.The electrical measure-ment shows TIA achieves 58 dBΩup to 12.7 GHz with a 180-fF off-chip photodetector.The optical measurement demonstrates a clear open eye of 20 Gb/s.The TIA dissipates 4 mW from a 1.2-V supply voltage.
文摘This study presents a hybrid algorithm obtained by combining a genetic algorithm (GA) with successive quadratic sequential programming (SQP), namely GA-SQP. GA is the main optimizer, whereas SQP is used to refine the results of GA, further improving the solution quality. The problem formulation is done in the framework named RUNE (fRamework for aUtomated aNalog dEsign), which targets solving nonlinear mono-objective and multi-objective optimization problems for analog circuits design. Two circuits are presented: a transimpedance amplifier (TIA) and an optical driver (Driver), which are both part of an Optical Network-on-Chip (ONoC). Furthermore, convergence characteristics and robustness of the proposed method have been explored through comparison with results obtained with SQP algorithm. The outcome is very encouraging and suggests that the hybrid proposed method is very efficient in solving analog design problems.
文摘The design and measurement of a snap-shot mode cryogenic readout circuit（ROIC） for GaAs/AlGaAs QWIP FPAs was reported.CTIA input circuits with pixei level built-in electronic injection transistors were proposed to test the chip before assembly with a detector array.Design optimization techniques for cryogenic and low power are analyzed.An experimental ROIC chip of a 128×128 array was fabricated in 0.35μm CMOS technology.Measurements showed that the ROIC could operate at 77 K with low power dissipation of 35 mW.The chip has a pixel charge capacity of 2.57×10^6 electrons and transimpedance of 1.4×10^7Ω.Measurements showed that the transimpedance non-uniformity was less than 5%with a 10 MHz readout speed and a 3.3 V supply voltage.
基金Project supported by the National Defense Pre-research Fund of China (Grant No. 50405050303)the Natural Science Foundation of Jiangsu Province of China (Grant No. BK2009049)
文摘There are certain limitations in the application of uncooled focal plane array （FPA） detector due to the lack of an effective response model which reliably transforms the target temperature to analog output voltage. This paper establishes the response model of microbolometer through researching the detection theory of microbolometer and the heat balance equation under the condition of the pulsed voltage bias. In the establishing process, we simplified the heat balance equation to acquire a simple answer. The experimental data show that, in the temperature dynamic range of 30 K, the biggest tolerance between the model data and the experiment data is 0.2 K; while in the temperature dynamic range of 100 K, it is 1 K. This model can reflect the real response of the microbolometer with only small differences which are acceptable in engineering applications.
基金supported in part by Research and Development Program in Key Areas of Guangdong Province under Grant 2019B010116002in part by the National Natural Science Foundation of China under Grant 62074074in part by the Science and Technology Plan of Shenzhen under Grants JCYJ20190809142017428 and JCYJ20200109141225025。
文摘This paper presents a 26-Gb/s CMOS optical receiver that is fabricated in 65-nm technology. It consists of a tripleinductive transimpedance amplifier(TIA), direct current(DC) offset cancellation circuits, 3-stage gm-TIA variable-gain amplifiers(VGA), and a reference-less clock and data recovery(CDR) circuit with built-in equalization technique. The TIA/VGA frontend measurement results demonstrate 72-dB? transimpedance gain, 20.4-GHz-3-dB bandwidth, and 12-dB DC gain tuning range. The measurements of the VGA’s resistive networks also demonstrate its efficient capability of overcoming the voltage and temperature variations. The CDR adopts a full-rate topology with 12-dB imbedded equalization tuning range. Optical measurements of this chipset achieve a 10-12 BER at 26 Gb/s for a 2;-1 PRBS input with a-7.3-dBm input sensitivity. The measurement results with a 10-dB @ 13 GHz attenuator also demonstrate the effectiveness of the gain tuning capability and the built-in equalization. The entire system consumes 140 mW from a 1/1.2-V supply.
基金The National Natural Science Foundation of China(No.61306069)
文摘A 12-Gbit/s low-power,wide-bandwidh CMOS(complementary metal oxide semiconductor)dual negative feedback feed-forward common gate(DNFFCG)differential trans-impedance amplifier(TIA)is presented for the veryshort-reach(VSR)optoelectronic integrated circuit(OEIC)receiver.The dominant pole of the input node is shifted up to a high frequency,and thus the bandwidth of the CMOS DNFFCG TIA is improved.Besides,two negative feedback loops are used to reduce the input impedance and further increase the bandwidth.The proposed TIA was fabricated using TSMC 0.18 jxm CMOS technology.The whole circuit has a compact chip area,the core area of which is only 0.003 6 mm2.The power consumption is 14.6 mW excluding 2-stage differential buffers.The test results indicate that the 3 dB bandwidth of 9 GHz is achieved with a 1 8 V supply voltage and its trans-impedance gain is 49.2 dBH.The measured average equivalent input noise current density is 28.1 pA H z12.Under the same process conditions,the DNFFCG has better gain bandwidth product compared with those in the published papers.
基金The Key Technology Research and Development Program of Jiangsu Province ( No. BE2008128)
文摘A 10 Gbit/s burst-mode preamplifier is designed for passive optical networks （PONs）. To achieve a high dynamic range and fast response, the circuit is DC coupled, and a feed-back type peak detector is designed to perform auto-gaincontrol and threshold extraction. Regulated cascade （RGC） architecture is exploited as the input stage to reduce the input impedance of the circuit and isolate the large parasitic capacitance including the photodiode capacitance from the determination pole, thus increasing the bandwidth. This preamplifier is implemented using the low-cost 0. 13 ixm CMOS technology. The die area is 425 μm × 475 μm and the total power dissipation is 23.4 mW. The test results indicate that the preamplifier can work at a speed from 1.25 to 10.312 5 Gbit/s, providing a high transimpedance gain of 64.0 dBΩ and a low gain of 54. 6 dBl2 with a dynamic input range of over 22.9 dB. The equivalent input noise current is 23. 4 pA/ Hz1/2. The proposed burst amplifier satisfies related specifications defined in 10G-EPON and XG-PON standards.
