The development of VLSI technology results in the dramatically improvement of the performance of integrated circuits. However, it brings more challenges to the aspect of reliability. Integrated circuits become more su...The development of VLSI technology results in the dramatically improvement of the performance of integrated circuits. However, it brings more challenges to the aspect of reliability. Integrated circuits become more susceptible to soft errors. Therefore, it is imperative to study the reliability of circuits under the soft error. This paper implements three probabilistic methods (two pass, error propagation probability, and probabilistic transfer matrix) for estimating gate-level circuit reliability on PC. The functions and performance of these methods are compared by experiments using ISCAS85 and 74-series circuits.展开更多
Soft errors have become a critical challenge as a result of technology scaling. Existing circuit-hardening techniques are commonly associated with prohibitive overhead of performance, area, and power. However,evaluati...Soft errors have become a critical challenge as a result of technology scaling. Existing circuit-hardening techniques are commonly associated with prohibitive overhead of performance, area, and power. However,evaluating the influence of soft errors in Flip-Flops(FFs) on the failure of circuit is a difficult verification problem.Here, we proposed a novel flip-flop soft-error failure rate analysis methodology using a formal method with respect to application behaviors. Approach and optimization techniques to implement the proposed methodology based on the given formula using Sequential Equivalence Checking(SEC) are introduced. The proposed method combines the advantage of formal technique-based approaches in completeness and the advantage of application behaviors in accuracy to differentiate vulnerability of components. As a result, the FFs in a circuit are sorted by their failure rates, and designers can use this information to perform optimal hardening of selected sequential components against soft errors. Experimental results of an implementation of a SpaceWire end node and the largest ISCAS’89 benchmark sequential circuits indicate the feasibility and potential scalability of our approach. A case study on an instruction decoder of a practical 32-bit microprocessor demonstrates the applicability of our method.展开更多
In this paper, a simulation tool named the neutron-induced single event effect predictive platform（NSEEP^2） is proposed to reveal the mechanism of atmospheric neutron-induced single event effect（SEE） in an electro...In this paper, a simulation tool named the neutron-induced single event effect predictive platform（NSEEP^2） is proposed to reveal the mechanism of atmospheric neutron-induced single event effect（SEE） in an electronic device, based on heavy-ion data and Monte-Carlo neutron transport simulation. The detailed metallization architecture and sensitive volume topology of a nanometric static random access memory（SRAM） device can be considered to calculate the real-time soft error rate（RTSER） in the applied environment accurately. The validity of this tool is verified by real-time experimental results. In addition, based on the NSEEP^2, RTSERs of 90 nm–32 nm silicon on insulator（SOI） and bulk SRAM device under various ambient conditions are predicted and analyzed to evaluate the neutron SEE sensitivity and reveal the underlying mechanism. It is found that as the feature size shrinks, the change trends of neutron SEE sensitivity of bulk and SOI technologies are opposite, which can be attributed to the different MBU performances. The RTSER of bulk technology is always 2.8–64 times higher than that of SOI technology, depending on the technology node, solar activity, and flight height.展开更多
基金the National Basic Research and Development (973) Program of China (No. 2005CB321604)the National Natural Science Foundation of China (No. 90207021)
文摘The development of VLSI technology results in the dramatically improvement of the performance of integrated circuits. However, it brings more challenges to the aspect of reliability. Integrated circuits become more susceptible to soft errors. Therefore, it is imperative to study the reliability of circuits under the soft error. This paper implements three probabilistic methods (two pass, error propagation probability, and probabilistic transfer matrix) for estimating gate-level circuit reliability on PC. The functions and performance of these methods are compared by experiments using ISCAS85 and 74-series circuits.
基金supported by the National Key Basic R&D Program (973) of China (No. 2017YFB1001802)
文摘Soft errors have become a critical challenge as a result of technology scaling. Existing circuit-hardening techniques are commonly associated with prohibitive overhead of performance, area, and power. However,evaluating the influence of soft errors in Flip-Flops(FFs) on the failure of circuit is a difficult verification problem.Here, we proposed a novel flip-flop soft-error failure rate analysis methodology using a formal method with respect to application behaviors. Approach and optimization techniques to implement the proposed methodology based on the given formula using Sequential Equivalence Checking(SEC) are introduced. The proposed method combines the advantage of formal technique-based approaches in completeness and the advantage of application behaviors in accuracy to differentiate vulnerability of components. As a result, the FFs in a circuit are sorted by their failure rates, and designers can use this information to perform optimal hardening of selected sequential components against soft errors. Experimental results of an implementation of a SpaceWire end node and the largest ISCAS’89 benchmark sequential circuits indicate the feasibility and potential scalability of our approach. A case study on an instruction decoder of a practical 32-bit microprocessor demonstrates the applicability of our method.
基金supported by the National Natural Science Foundation of China(Grant No.11505033)the Science and Technology Research Project of Guangdong Province,China(Grant Nos.2015B090901048 and 2017B090901068)the Science and Technology Plan Project of Guangzhou,China(Grant No.201707010186)
文摘In this paper, a simulation tool named the neutron-induced single event effect predictive platform（NSEEP^2） is proposed to reveal the mechanism of atmospheric neutron-induced single event effect（SEE） in an electronic device, based on heavy-ion data and Monte-Carlo neutron transport simulation. The detailed metallization architecture and sensitive volume topology of a nanometric static random access memory（SRAM） device can be considered to calculate the real-time soft error rate（RTSER） in the applied environment accurately. The validity of this tool is verified by real-time experimental results. In addition, based on the NSEEP^2, RTSERs of 90 nm–32 nm silicon on insulator（SOI） and bulk SRAM device under various ambient conditions are predicted and analyzed to evaluate the neutron SEE sensitivity and reveal the underlying mechanism. It is found that as the feature size shrinks, the change trends of neutron SEE sensitivity of bulk and SOI technologies are opposite, which can be attributed to the different MBU performances. The RTSER of bulk technology is always 2.8–64 times higher than that of SOI technology, depending on the technology node, solar activity, and flight height.
