Silicon on insulator (SOI) technology permits a good solution to the miniaturization as the MOSFET size scales down. This paper is about to compare the electrical performance of nanoscale FD-SOI MOSFET at various gate...Silicon on insulator (SOI) technology permits a good solution to the miniaturization as the MOSFET size scales down. This paper is about to compare the electrical performance of nanoscale FD-SOI MOSFET at various gate lengths. The performance is compared and contrasted with the help of threshold voltage, subthreshold slope, on-state current and leakage current. Interestingly, by decreasing the gate length, the leakage current and on-state current are increased but the threshold voltage is decreased and the sub-threshold slope is degraded. Silvaco two-dimensional simulations are used to analyze the performance of the proposed structures.展开更多
The steep sub-threshold swing of a tunneling field-effect transistor(TFET)makes it one of the best candidates for lowpower nanometer devices.However,the low driving capability of TFETs prevents their application in in...The steep sub-threshold swing of a tunneling field-effect transistor(TFET)makes it one of the best candidates for lowpower nanometer devices.However,the low driving capability of TFETs prevents their application in integrated circuits.In this study,an innovative gate-all-around(GAA)TFET,which represents a negative capacitance GAA gate-to-source overlap TFET(NCGAA-SOL-TFET),is proposed to increase the driving current.The proposed NCGAA-SOL-TFET is developed based on technology computer-aided design(TCAD)simulations.The proposed structure can solve the problem of the insufficient driving capability of conventional TFETs and is suitable for sub-3-nm nodes.In addition,due to the negative capacitance effect,the surface potential of the channel can be amplified,thus enhancing the driving current.The gateto-source overlap(SOL)technique is used for the first time in an NCGAA-TFET to increase the band-to-band tunneling rate and tunneling area at the silicon-germanium heterojunction.By optimizing the design of the proposed structure via adjusting the SOL length and the ferroelectric layer thickness,a sufficiently large on-state current of 17.20μA can be achieved and the threshold voltage can be reduced to 0.31 V with a sub-threshold swing of 44.98 mV/decade.Finally,the proposed NCGAA-SOL-TFET can overcome the Boltzmann limit-related problem,achieving a driving current that is comparable to that of the traditional complementary metal-oxide semiconductor devices.展开更多
With the development of silicon photomultiplier(SiPM)technology,front-end electronics for SiPM signal processing have been highly sought after in various fields.A compact 64-channel front-end electronics(FEE)system ac...With the development of silicon photomultiplier(SiPM)technology,front-end electronics for SiPM signal processing have been highly sought after in various fields.A compact 64-channel front-end electronics(FEE)system achieved by fieldprogrammable gate array-based charge-to-digital converter(FPGA-QDC)technology was built and developed.The FEE consists of an analog board and FPGA board.The analog board incorporates commercial amplifiers,resistors,and capacitors.The FPGA board is composed of a low-cost FPGA.The electronics performance of the FEE was evaluated in terms of noise,linearity,and uniformity.A positron emission tomography(PET)detector with three different readout configurations was designed to validate the readout capability of the FEE for SiPM-based detectors.The PET detector was made of a 15×15 lutetium–yttrium oxyorthosilicate(LYSO)crystal array directly coupled with a SiPM array detector.The experimental results show that FEE can process dual-polarity charge signals from the SiPM detectors.In addition,it shows a good energy resolution for 511-keV gamma photons under the dual-end readout for the LYSO crystal array irradiated by a Na-22 source.Overall,the FEE based on FPGA-QDC shows promise for application in SiPM-based radiation detectors.展开更多
The hot-carrier effect charactenstic in a deep submicron partially depleted SOI NMOSFET is investigated. Obvious hot-carrier degradation is observed under off-state stress.The hot-carrier damage is supposed to be indu...The hot-carrier effect charactenstic in a deep submicron partially depleted SOI NMOSFET is investigated. Obvious hot-carrier degradation is observed under off-state stress.The hot-carrier damage is supposed to be induced by the parasitic bipolar effects of a float SOI device.The back channel also suffers degradation from the hot carrier in the drain depletion region as well as the front channel.At low gate voltage,there is a hump in the sub-threshold curve of the back gate transistor,and it does not shift in the same way as the main transistor under stress.While under the same condition,there is a more severe hot-carrier effect with a shorter channel transistor. The reasons for those phenomena are discussed in detail.展开更多
In order to improve the bias stability of the micro-electro mechanical system（MEMS） gyroscope and reduce the impact on the bias from environmental temperature,a digital signal processing method is described for impr...In order to improve the bias stability of the micro-electro mechanical system（MEMS） gyroscope and reduce the impact on the bias from environmental temperature,a digital signal processing method is described for improving the accuracy of the drive phase in the gyroscope drive mode.Through the principle of bias signal generation,it can be concluded that the deviation of the drive phase is the main factor affecting the bias stability.To fulfill the purpose of precise drive phase control,a digital signal processing circuit based on the field-programmable gate array（FPGA） with the phase-lock closed-loop control method is described and a demodulation method for phase error suppression is given.Compared with the analog circuit,the bias drift is largely reduced in the new digital circuit and the bias stability is improved from 60 to 19 °/h.The new digital control method can greatly increase the drive phase accuracy,and thus improve the bias stability.展开更多
A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs.Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI...A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs.Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI MOSFETs is also carried out.Finally this work is concluded by modeling the cut-off frequency, which is one of the main figures of merit for analog/RF performance for double-gate fully depleted nanoscale SOI MOSFETs.The results of the modeling are compared with those obtained by a 2D ATLAS device simulator to verify the accuracy of the proposed model.展开更多
A 4H-SiC trench gate metal-oxide-semiconductor field-effect transistor(UMOSFET)with semi-super-junction shiel-ded structure(SS-UMOS)is proposed and compared with conventional trench MOSFET(CT-UMOS)in this work.The adv...A 4H-SiC trench gate metal-oxide-semiconductor field-effect transistor(UMOSFET)with semi-super-junction shiel-ded structure(SS-UMOS)is proposed and compared with conventional trench MOSFET(CT-UMOS)in this work.The advantage of the proposed structure is given by comprehensive study of the mechanism of the local semi-super-junction structure at the bottom of the trench MOSFET.In particular,the influence of the bias condition of the p-pillar at the bottom of the trench on the static and dynamic performances of the device is compared and revealed.The on-resistance of SS-UMOS with grounded(G)and ungrounded(NG)p-pillar is reduced by 52%(G)and 71%(NG)compared to CT-UMOS,respectively.Additionally,gate ox-ide in the GSS-UMOS is fully protected by the p-shield layer as well as semi-super-junction structure under the trench and p-base regions.Thus,a reduced electric-field of 2 MV/cm can be achieved at the corner of the p-shield layer.However,the quasi-intrinsic protective layer cannot be formed in NGSS-UMOS due to the charge storage effect in the floating p-pillar,resulting in a large electric field of 2.7 MV/cm at the gate oxide layer.Moreover,the total switching loss of GSS-UMOS is 1.95 mJ/cm2 and is reduced by 18%compared with CT-UMOS.On the contrary,the NGSS-UMOS has the slowest overall switching speed due to the weakened shielding effect of the p-pillar and the largest gate-to-drain capacitance among the three.The proposed GSS-UMOS plays an important role in high-voltage and high-frequency applications,and will provide a valuable idea for device design and circuit applications.展开更多
This article investigates an improved 4H-SiC trench gate metal–oxide–semiconductor field-effect transistor(MOSFET)(UMOSFET)fitted with a super-junction(SJ)shielded region.The modified structure is composed of two n-...This article investigates an improved 4H-SiC trench gate metal–oxide–semiconductor field-effect transistor(MOSFET)(UMOSFET)fitted with a super-junction(SJ)shielded region.The modified structure is composed of two n-type conductive pillars,three p-type conductive pillars,an oxide trench under the gate,and a light n-type current spreading layer(NCSL)under the p-body.The n-type conductive pillars and the light n-type current spreading layer provide two paths to and promote the diffusion of a transverse current in the epitaxial layer,thus improving the specific on-resistance(R_(on,sp)).There are three p-type pillars in the modified structure,with the p-type pillars on both sides playing the same role.The p-type conductive pillars relieve the electric field(E-field)in the corner of the trench bottom.Two-dimensional simulation(silvaco TCAD)indicates that Ron,sp of the modified structure,and breakdown voltage(V_(BR))are improved by 22.2%and 21.1%respectively,while the maximum figure of merit(FOM=V_(BR)^(2)/R_(on,sp)) is improved by 79.0%.Furthermore,the improved structure achieves a light smaller low gate-to-drain charge(Q_(gd))and when compared with the conventional UMOSFET(conventional-UMOS),it displays great advantages for reducing the switching energy loss.These advantages are due to the fact that the p-type conductive pillars and n-type conductive pillars configured under the gate provide a substantial charge balance,which also enables the charge carriers to be extracted quickly.In the end,under the condition of the same total charge quantity,the simulation comparison of gate charge and OFF-state characteristics between Gaussdoped structure and uniform-doped structure shows that Gauss-doped structure increases the V_(BR)of the device without degradation of dynamic performance.展开更多
The incubation layer with amorphous structure between the substrate and crystalline layer may obviously affect the performance for a microcrystalline Si thin film transistor (μc-Si TFT),especially for the bottom gate...The incubation layer with amorphous structure between the substrate and crystalline layer may obviously affect the performance for a microcrystalline Si thin film transistor (μc-Si TFT),especially for the bottom gate TFT(BG-TFT).It is found that decreasing the ratio of SiH 4/(H 2+SiH 4) is an effective way to decrease the incubation layer thickness of μc-Si directly deposited by VHF PECVD without any further thermal or laser treatment.Based on the μc-Si with a thin incubation layer,the BG-TFT with Al/SiN x/μc-Si/n+-μc-Si/Al structure is fabricated.The ratio of on-state current to off-state current is up to 106,the mobility is around 0.7cm2/(V·s),and the threshold voltage is about 5V.展开更多
A low specific on-resistance （RS,on） silicon-on-insulator （SOI） trench MOSFET （nmtal-oxide-semiconductor-field- effect-transistor） with a reduced cell pitch is proposed. The lateral MOSFET features multiple tren...A low specific on-resistance （RS,on） silicon-on-insulator （SOI） trench MOSFET （nmtal-oxide-semiconductor-field- effect-transistor） with a reduced cell pitch is proposed. The lateral MOSFET features multiple trenches： two oxide trenches in the drift region and a trench gate extended to the buried oxide （BOX） （SOI MT MOSFET）. Firstly, the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si; secondly, the oxide trenches cause multiple=directional depletion, which improves the electric field distribution and enhances the reduced surface field （RESURF） effect in the SOI layer. Both of them result in a high breakdown voltage （BV）. Thirdly, the oxide trenches cause the drift region to be folded in the vertical direction, leading to a shortened cell pitch and a reduced Rs,on. Fourthly, the trench gate extended to the BOX further reduces RS,on, owing to the electron accumulation layer. The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal-oxide semiconductor （LDMOS） to 632 V at the same half cell pitch of 21.5 μm, and RS,on decreases from 419 mΩ cm2 to 36.6 mΩ. cm2. The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.展开更多
基金supported by the National Natural Science Foundation of China(22034003,21974059,and 22174063)the Excellent Research Program of Nanjing University(ZYJH004)the State Key Laboratory of Analytical Chemistry for Life Science(5431ZZXM2203)。
文摘Silicon on insulator (SOI) technology permits a good solution to the miniaturization as the MOSFET size scales down. This paper is about to compare the electrical performance of nanoscale FD-SOI MOSFET at various gate lengths. The performance is compared and contrasted with the help of threshold voltage, subthreshold slope, on-state current and leakage current. Interestingly, by decreasing the gate length, the leakage current and on-state current are increased but the threshold voltage is decreased and the sub-threshold slope is degraded. Silvaco two-dimensional simulations are used to analyze the performance of the proposed structures.
基金supported by the Zhejiang Provincial Natural Science Foundation of China(Grant No.LY22F040001)the National Natural Science Foundation of China(Grant No.62071160)the Graduate Scientific Research Foundation of Hangzhou Dianzi University。
文摘The steep sub-threshold swing of a tunneling field-effect transistor(TFET)makes it one of the best candidates for lowpower nanometer devices.However,the low driving capability of TFETs prevents their application in integrated circuits.In this study,an innovative gate-all-around(GAA)TFET,which represents a negative capacitance GAA gate-to-source overlap TFET(NCGAA-SOL-TFET),is proposed to increase the driving current.The proposed NCGAA-SOL-TFET is developed based on technology computer-aided design(TCAD)simulations.The proposed structure can solve the problem of the insufficient driving capability of conventional TFETs and is suitable for sub-3-nm nodes.In addition,due to the negative capacitance effect,the surface potential of the channel can be amplified,thus enhancing the driving current.The gateto-source overlap(SOL)technique is used for the first time in an NCGAA-TFET to increase the band-to-band tunneling rate and tunneling area at the silicon-germanium heterojunction.By optimizing the design of the proposed structure via adjusting the SOL length and the ferroelectric layer thickness,a sufficiently large on-state current of 17.20μA can be achieved and the threshold voltage can be reduced to 0.31 V with a sub-threshold swing of 44.98 mV/decade.Finally,the proposed NCGAA-SOL-TFET can overcome the Boltzmann limit-related problem,achieving a driving current that is comparable to that of the traditional complementary metal-oxide semiconductor devices.
基金supported by the Natural Science Foundation of Shandong Province (No. ZR2022QA039)the Program of Qilu Young Scholars of Shandong University
文摘With the development of silicon photomultiplier(SiPM)technology,front-end electronics for SiPM signal processing have been highly sought after in various fields.A compact 64-channel front-end electronics(FEE)system achieved by fieldprogrammable gate array-based charge-to-digital converter(FPGA-QDC)technology was built and developed.The FEE consists of an analog board and FPGA board.The analog board incorporates commercial amplifiers,resistors,and capacitors.The FPGA board is composed of a low-cost FPGA.The electronics performance of the FEE was evaluated in terms of noise,linearity,and uniformity.A positron emission tomography(PET)detector with three different readout configurations was designed to validate the readout capability of the FEE for SiPM-based detectors.The PET detector was made of a 15×15 lutetium–yttrium oxyorthosilicate(LYSO)crystal array directly coupled with a SiPM array detector.The experimental results show that FEE can process dual-polarity charge signals from the SiPM detectors.In addition,it shows a good energy resolution for 511-keV gamma photons under the dual-end readout for the LYSO crystal array irradiated by a Na-22 source.Overall,the FEE based on FPGA-QDC shows promise for application in SiPM-based radiation detectors.
文摘The hot-carrier effect charactenstic in a deep submicron partially depleted SOI NMOSFET is investigated. Obvious hot-carrier degradation is observed under off-state stress.The hot-carrier damage is supposed to be induced by the parasitic bipolar effects of a float SOI device.The back channel also suffers degradation from the hot carrier in the drain depletion region as well as the front channel.At low gate voltage,there is a hump in the sub-threshold curve of the back gate transistor,and it does not shift in the same way as the main transistor under stress.While under the same condition,there is a more severe hot-carrier effect with a shorter channel transistor. The reasons for those phenomena are discussed in detail.
基金The National Natural Science Foundation of China (No.60974116)the Research Fund of Aeronautics Science (No. 20090869007)Specialized Research Fund for the Doctoral Program of Higher Education(No. 200802861063)
文摘In order to improve the bias stability of the micro-electro mechanical system（MEMS） gyroscope and reduce the impact on the bias from environmental temperature,a digital signal processing method is described for improving the accuracy of the drive phase in the gyroscope drive mode.Through the principle of bias signal generation,it can be concluded that the deviation of the drive phase is the main factor affecting the bias stability.To fulfill the purpose of precise drive phase control,a digital signal processing circuit based on the field-programmable gate array（FPGA） with the phase-lock closed-loop control method is described and a demodulation method for phase error suppression is given.Compared with the analog circuit,the bias drift is largely reduced in the new digital circuit and the bias stability is improved from 60 to 19 °/h.The new digital control method can greatly increase the drive phase accuracy,and thus improve the bias stability.
文摘A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs.Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI MOSFETs is also carried out.Finally this work is concluded by modeling the cut-off frequency, which is one of the main figures of merit for analog/RF performance for double-gate fully depleted nanoscale SOI MOSFETs.The results of the modeling are compared with those obtained by a 2D ATLAS device simulator to verify the accuracy of the proposed model.
基金supported by the National Natural Science Foundation of China(Grant No.62104222)the Natural Science Foundation of Fujian Province of China for Distinguished Young Scholars(Grant No.2020J06002)+3 种基金the Science and Technology Project of Fujian Province of China(Grant No.2020I0001)the Science and Technology Key Projects of Xiamen(Grant No.3502ZCQ20191001)Shenzhen Science and Technology Program(Grant No.JSGG20201102-155800003)Jiangxi Provincial Natural Science Foundation(Grant No.20212ACB212005).
文摘A 4H-SiC trench gate metal-oxide-semiconductor field-effect transistor(UMOSFET)with semi-super-junction shiel-ded structure(SS-UMOS)is proposed and compared with conventional trench MOSFET(CT-UMOS)in this work.The advantage of the proposed structure is given by comprehensive study of the mechanism of the local semi-super-junction structure at the bottom of the trench MOSFET.In particular,the influence of the bias condition of the p-pillar at the bottom of the trench on the static and dynamic performances of the device is compared and revealed.The on-resistance of SS-UMOS with grounded(G)and ungrounded(NG)p-pillar is reduced by 52%(G)and 71%(NG)compared to CT-UMOS,respectively.Additionally,gate ox-ide in the GSS-UMOS is fully protected by the p-shield layer as well as semi-super-junction structure under the trench and p-base regions.Thus,a reduced electric-field of 2 MV/cm can be achieved at the corner of the p-shield layer.However,the quasi-intrinsic protective layer cannot be formed in NGSS-UMOS due to the charge storage effect in the floating p-pillar,resulting in a large electric field of 2.7 MV/cm at the gate oxide layer.Moreover,the total switching loss of GSS-UMOS is 1.95 mJ/cm2 and is reduced by 18%compared with CT-UMOS.On the contrary,the NGSS-UMOS has the slowest overall switching speed due to the weakened shielding effect of the p-pillar and the largest gate-to-drain capacitance among the three.The proposed GSS-UMOS plays an important role in high-voltage and high-frequency applications,and will provide a valuable idea for device design and circuit applications.
基金the National Natural Science Foundation of China(Grant Nos.61774052 and 61904045)the Youth Foundation of the Education Department of Jiangxi Province,China(Grant No.GJJ191154)the Youth Foundation of Ping Xiang University,China(Grant No.2018D0230).
文摘This article investigates an improved 4H-SiC trench gate metal–oxide–semiconductor field-effect transistor(MOSFET)(UMOSFET)fitted with a super-junction(SJ)shielded region.The modified structure is composed of two n-type conductive pillars,three p-type conductive pillars,an oxide trench under the gate,and a light n-type current spreading layer(NCSL)under the p-body.The n-type conductive pillars and the light n-type current spreading layer provide two paths to and promote the diffusion of a transverse current in the epitaxial layer,thus improving the specific on-resistance(R_(on,sp)).There are three p-type pillars in the modified structure,with the p-type pillars on both sides playing the same role.The p-type conductive pillars relieve the electric field(E-field)in the corner of the trench bottom.Two-dimensional simulation(silvaco TCAD)indicates that Ron,sp of the modified structure,and breakdown voltage(V_(BR))are improved by 22.2%and 21.1%respectively,while the maximum figure of merit(FOM=V_(BR)^(2)/R_(on,sp)) is improved by 79.0%.Furthermore,the improved structure achieves a light smaller low gate-to-drain charge(Q_(gd))and when compared with the conventional UMOSFET(conventional-UMOS),it displays great advantages for reducing the switching energy loss.These advantages are due to the fact that the p-type conductive pillars and n-type conductive pillars configured under the gate provide a substantial charge balance,which also enables the charge carriers to be extracted quickly.In the end,under the condition of the same total charge quantity,the simulation comparison of gate charge and OFF-state characteristics between Gaussdoped structure and uniform-doped structure shows that Gauss-doped structure increases the V_(BR)of the device without degradation of dynamic performance.
文摘The incubation layer with amorphous structure between the substrate and crystalline layer may obviously affect the performance for a microcrystalline Si thin film transistor (μc-Si TFT),especially for the bottom gate TFT(BG-TFT).It is found that decreasing the ratio of SiH 4/(H 2+SiH 4) is an effective way to decrease the incubation layer thickness of μc-Si directly deposited by VHF PECVD without any further thermal or laser treatment.Based on the μc-Si with a thin incubation layer,the BG-TFT with Al/SiN x/μc-Si/n+-μc-Si/Al structure is fabricated.The ratio of on-state current to off-state current is up to 106,the mobility is around 0.7cm2/(V·s),and the threshold voltage is about 5V.
基金supported by the National Natural Science Foundation of China (Grant Nos. 60806025 and 60976060)the Science Fund of the National Laboratory of Analog Integrated Circuit (Grant No. 9140C0903070904)the Innovation Foundation of the State Key Laboratory of Electronic Thin Films and Integrated Devices (Grant No. CXJJ201004)
文摘A low specific on-resistance （RS,on） silicon-on-insulator （SOI） trench MOSFET （nmtal-oxide-semiconductor-field- effect-transistor） with a reduced cell pitch is proposed. The lateral MOSFET features multiple trenches： two oxide trenches in the drift region and a trench gate extended to the buried oxide （BOX） （SOI MT MOSFET）. Firstly, the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si; secondly, the oxide trenches cause multiple=directional depletion, which improves the electric field distribution and enhances the reduced surface field （RESURF） effect in the SOI layer. Both of them result in a high breakdown voltage （BV）. Thirdly, the oxide trenches cause the drift region to be folded in the vertical direction, leading to a shortened cell pitch and a reduced Rs,on. Fourthly, the trench gate extended to the BOX further reduces RS,on, owing to the electron accumulation layer. The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal-oxide semiconductor （LDMOS） to 632 V at the same half cell pitch of 21.5 μm, and RS,on decreases from 419 mΩ cm2 to 36.6 mΩ. cm2. The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.
