Boolean algebra successfully describes the logical behavior of a digital circuit, and has been widely used in electronic circuit design and test With the development of high speed VLSIs it is a drawback for Boolean al...Boolean algebra successfully describes the logical behavior of a digital circuit, and has been widely used in electronic circuit design and test With the development of high speed VLSIs it is a drawback for Boolean algebra to be unable to describe circuit timing behavior. Therefore a Boolean process is defined as a family of Boolean van ables relevant to the time parameter t. A real-valued sample of a Boolean process is a waveform. Waveform functions can be manipulated formally by using mathematical tools. The distance, difference and limit of a waveform polynomial are defined, and a sufficient and necessary condition of the limit existence is presented. Based on this, the concept of sensitization is redefined precisely to demonstrate the potential and wide application possibility The new definition is very different from the traditional one, and has an impact on determining the sensitizable paths with maximum or minimum length, and false paths, and then designing and testing high performance circuits展开更多
Delay considerttion has been a major issue in design and test of high performance digital circuits . The assumption of input signal change occurring only when all internal nodes are stable restricts the increase of cl...Delay considerttion has been a major issue in design and test of high performance digital circuits . The assumption of input signal change occurring only when all internal nodes are stable restricts the increase of clock frequency. It is no longer true for wave pipelining circuits. However, previous logical delay models are based on the assumption. In addition, the stable time of a robust delay test generally depends on the longest sensitizable path delay. Thus , a new delay model is desirable. This paper explores the necessity first. Then, Boolean process to analytically describe the logical and timing behavior of a digital circuit is reviewed . The concept of sensitization is redefined precisely in this paper. Based on the new concept of sensitization, an analytical delay model is introduced . As a result , many untestable delay faults under the logical delay model can be tested if the output waveforms can be sampled at more time points. The longest sensitiaable path length is computed for circuit design and delay test .展开更多
基金Project supported by the National Natural Science Foundation of China.
文摘Boolean algebra successfully describes the logical behavior of a digital circuit, and has been widely used in electronic circuit design and test With the development of high speed VLSIs it is a drawback for Boolean algebra to be unable to describe circuit timing behavior. Therefore a Boolean process is defined as a family of Boolean van ables relevant to the time parameter t. A real-valued sample of a Boolean process is a waveform. Waveform functions can be manipulated formally by using mathematical tools. The distance, difference and limit of a waveform polynomial are defined, and a sufficient and necessary condition of the limit existence is presented. Based on this, the concept of sensitization is redefined precisely to demonstrate the potential and wide application possibility The new definition is very different from the traditional one, and has an impact on determining the sensitizable paths with maximum or minimum length, and false paths, and then designing and testing high performance circuits
文摘Delay considerttion has been a major issue in design and test of high performance digital circuits . The assumption of input signal change occurring only when all internal nodes are stable restricts the increase of clock frequency. It is no longer true for wave pipelining circuits. However, previous logical delay models are based on the assumption. In addition, the stable time of a robust delay test generally depends on the longest sensitizable path delay. Thus , a new delay model is desirable. This paper explores the necessity first. Then, Boolean process to analytically describe the logical and timing behavior of a digital circuit is reviewed . The concept of sensitization is redefined precisely in this paper. Based on the new concept of sensitization, an analytical delay model is introduced . As a result , many untestable delay faults under the logical delay model can be tested if the output waveforms can be sampled at more time points. The longest sensitiaable path length is computed for circuit design and delay test .
