A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-andhold amplifier （SHA） is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to allevi...A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-andhold amplifier （SHA） is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to alleviate the clock skew effect. On-chip bias current is programmable to achieve low power dissipation at different sampling rates. Particularly, drain-to-source voltages in the operational amplifiers （opamps） are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in 0.18-μm 1P6M CMOS technology. With a 2.4-MHz input, the measured peak SNDR and SFDR are 74.4 and 91.6 dB at 2.5 MSample/s, 74.3 and 85.4 dB at 8.0 MSample/s. It consumes 8.1, 21.6, 29.7, and 56.7 mW （including I/O drivers） when operating at 1.5, 2.5, 5.0, and 8.0 MSample/s with 2.7 V power supply, respectively. The chip occupies 3.2 mm^2, including I/O pads.展开更多
This paper proposes a new low power structure to improve the trade-off between the bandwidth and the power consumption of a programmable gain amplifier（PGA）.The PGA consists of three-stage amplifiers, which includes...This paper proposes a new low power structure to improve the trade-off between the bandwidth and the power consumption of a programmable gain amplifier（PGA）.The PGA consists of three-stage amplifiers, which includes a variable gain amplifier and DC offset cancellation circuits.The cutoff frequency of the DC offset cancellation circuits can be changed from 4 to 80 kHz.The chip was fabricated in 0.13μm CMOS technology. Measurement results showed that the gain of the PGA can be programmed from -5 to 60 dB.At the gain setting of 60 dB,the bandwidth can be tuned from 1 to 10 MHz,while the power consumption can be programmed from 850μA to 3.2 mA at a supply voltage of 1.2 V.Its in-band OIP3 result is at 14 dBm.展开更多
文摘A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-andhold amplifier （SHA） is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to alleviate the clock skew effect. On-chip bias current is programmable to achieve low power dissipation at different sampling rates. Particularly, drain-to-source voltages in the operational amplifiers （opamps） are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in 0.18-μm 1P6M CMOS technology. With a 2.4-MHz input, the measured peak SNDR and SFDR are 74.4 and 91.6 dB at 2.5 MSample/s, 74.3 and 85.4 dB at 8.0 MSample/s. It consumes 8.1, 21.6, 29.7, and 56.7 mW （including I/O drivers） when operating at 1.5, 2.5, 5.0, and 8.0 MSample/s with 2.7 V power supply, respectively. The chip occupies 3.2 mm^2, including I/O pads.
基金Project supported by the National High-Tech Research and Development Program of China(No.2009AA011606)the National Natural Science Foundation of China(No.60976023)
文摘This paper proposes a new low power structure to improve the trade-off between the bandwidth and the power consumption of a programmable gain amplifier（PGA）.The PGA consists of three-stage amplifiers, which includes a variable gain amplifier and DC offset cancellation circuits.The cutoff frequency of the DC offset cancellation circuits can be changed from 4 to 80 kHz.The chip was fabricated in 0.13μm CMOS technology. Measurement results showed that the gain of the PGA can be programmed from -5 to 60 dB.At the gain setting of 60 dB,the bandwidth can be tuned from 1 to 10 MHz,while the power consumption can be programmed from 850μA to 3.2 mA at a supply voltage of 1.2 V.Its in-band OIP3 result is at 14 dBm.
