A low-power 14-bit 150MS/s an- alog-to-digital converter (ADC) is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor shari...A low-power 14-bit 150MS/s an- alog-to-digital converter (ADC) is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter (MDAC) and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier (SHA) is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.展开更多
A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier (CTIA), and a 12 bit pipelined analog-to- digita...A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier (CTIA), and a 12 bit pipelined analog-to- digital converter (ADC), and is implemented in a 0.18μm standard CMOS process. Some special techniques, such as a "contact imaging" detecting method, pseudo-differential architecture, dummy photodiodes, and a T-type reset switch, are adopted to achieve low-level sensing application. Experiment results show that the Nwell/Psub photodiode with CTIA pixel achieves a sensitivity of 0.1 A/W at 515 nm and a dark current of 300 fA with 300 mV reverse biased voltage. The maximum differential and integral nonlinearity of the designed ADC are 0.8 LSB and 3 LSB, respectively. With an integrating time of 50 ms, this system is sensitive to the fluorescence emitted by the fluorescein solution with concentration as low as 20 ng/mL and can generate 7 fA photocurrent. This chip occupies 3 mm^2 and consumes 37 mW.展开更多
文章基于40 nm CMOS工艺设计一款12 Bit 1 GS/s射频采样的无采样保持放大电路的流水线ADC。首级采用了开关电容比较器结构提高了无采样保持放大电路带来的输入到Sub-ADC和MDAC采样通路的匹配度。后级Sub-ADC中采用对参考电压的预采样技...文章基于40 nm CMOS工艺设计一款12 Bit 1 GS/s射频采样的无采样保持放大电路的流水线ADC。首级采用了开关电容比较器结构提高了无采样保持放大电路带来的输入到Sub-ADC和MDAC采样通路的匹配度。后级Sub-ADC中采用对参考电压的预采样技术,缓解了后级比较器的压力。另外,首级处理3.5位量化精度,且理想级间增益为4,进一步缓解了首级MDAC对运放线性度、增益误差、输出信号电压摆幅的要求。采用高带宽高线性度的运放结构简化了模拟设计以及数字校准的复杂度。采样频率1 GHz,输入信号频率455 MHz,差分满摆幅1.2 V的情况下,经校准后ADC有效位数达到11.2位,信噪比70 d B,无杂散动态范围82 d B,总功耗约220 m W。展开更多
A 4 Gbps transmitter for a 12-bit 250 MSPS pipelined ADCs is presented. A low power current mode (CM) output driver with reverse scaling technique is proposed. A high speed, low power combined serializer is implemen...A 4 Gbps transmitter for a 12-bit 250 MSPS pipelined ADCs is presented. A low power current mode (CM) output driver with reverse scaling technique is proposed. A high speed, low power combined serializer is implemented to convert 12 bit parallel data into a serial data stream. The whole transmitter is used in a 12-bit 250 MSPS pipelined ADC for the digital output buffer and fabricated in 180 nm 1.8 V 1PSM CMOS technology. Test results show that the transmitter provides an eye height greater than 800 mV for data rates of both 2 Gbps and 4 Gbps, the 12-bit 250 MSPS ADC achieves the SNR of 69.92 dBFS and SFDR of 81.17 dB with 20.1 MHz input at full sampling speed. The ADC with the 4 Gbps transmitter consumes the power consumption of 395 mW, where the power consumption of transmitter is 75 mW. The ADC occupies an area of 2.5 × 3.2 mm2, where the active area of the transmitter block is 0.5× 1.2 mm2.展开更多
文摘设计了一种用于高速ADC中的全差分运算放大器。该运算放大器由主运放、4个辅助运放和一种改进型开关电容共模反馈电路组成,主运放采用折叠式共源共栅结构,并引入增益增强技术提高增益。采用SMIC 0.18μm,1.8 V工艺,在Cadence电路设计平台中利用Spectre仿真,结果表明:运放增益达到115 d B,单位增益带宽805 MHz,而功耗仅为10.5 m W,运放在8 ns的时间内可以达到0.01%的建立精度,可用于高速高精度流水线(Pipelined)ADC中。
基金supported by the Major National Science & Technology Program of China under Grant No.2012ZX03004004-002National High Technology Research and Development Program of China under Grant No. 2013AA014302
文摘A low-power 14-bit 150MS/s an- alog-to-digital converter (ADC) is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter (MDAC) and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier (SHA) is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.
基金supported by the Micro/Nanoelectronics Science and Technology Innovation Platform of Fudan University of China
文摘A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier (CTIA), and a 12 bit pipelined analog-to- digital converter (ADC), and is implemented in a 0.18μm standard CMOS process. Some special techniques, such as a "contact imaging" detecting method, pseudo-differential architecture, dummy photodiodes, and a T-type reset switch, are adopted to achieve low-level sensing application. Experiment results show that the Nwell/Psub photodiode with CTIA pixel achieves a sensitivity of 0.1 A/W at 515 nm and a dark current of 300 fA with 300 mV reverse biased voltage. The maximum differential and integral nonlinearity of the designed ADC are 0.8 LSB and 3 LSB, respectively. With an integrating time of 50 ms, this system is sensitive to the fluorescence emitted by the fluorescein solution with concentration as low as 20 ng/mL and can generate 7 fA photocurrent. This chip occupies 3 mm^2 and consumes 37 mW.
文摘文章基于40 nm CMOS工艺设计一款12 Bit 1 GS/s射频采样的无采样保持放大电路的流水线ADC。首级采用了开关电容比较器结构提高了无采样保持放大电路带来的输入到Sub-ADC和MDAC采样通路的匹配度。后级Sub-ADC中采用对参考电压的预采样技术,缓解了后级比较器的压力。另外,首级处理3.5位量化精度,且理想级间增益为4,进一步缓解了首级MDAC对运放线性度、增益误差、输出信号电压摆幅的要求。采用高带宽高线性度的运放结构简化了模拟设计以及数字校准的复杂度。采样频率1 GHz,输入信号频率455 MHz,差分满摆幅1.2 V的情况下,经校准后ADC有效位数达到11.2位,信噪比70 d B,无杂散动态范围82 d B,总功耗约220 m W。
基金supported by the National Science Foundation of China(No.61474092)Key Project of Natural Science of Anhui Provincial Department of Education(No.KJ2017A396)
文摘A 4 Gbps transmitter for a 12-bit 250 MSPS pipelined ADCs is presented. A low power current mode (CM) output driver with reverse scaling technique is proposed. A high speed, low power combined serializer is implemented to convert 12 bit parallel data into a serial data stream. The whole transmitter is used in a 12-bit 250 MSPS pipelined ADC for the digital output buffer and fabricated in 180 nm 1.8 V 1PSM CMOS technology. Test results show that the transmitter provides an eye height greater than 800 mV for data rates of both 2 Gbps and 4 Gbps, the 12-bit 250 MSPS ADC achieves the SNR of 69.92 dBFS and SFDR of 81.17 dB with 20.1 MHz input at full sampling speed. The ADC with the 4 Gbps transmitter consumes the power consumption of 395 mW, where the power consumption of transmitter is 75 mW. The ADC occupies an area of 2.5 × 3.2 mm2, where the active area of the transmitter block is 0.5× 1.2 mm2.