This paper presents the design and implementation of a current self-adjusted VCO with low power consumption. In the proposed VCO, a bottom PMOS current source instead of a top one is adopted to decrease the tail noise...This paper presents the design and implementation of a current self-adjusted VCO with low power consumption. In the proposed VCO, a bottom PMOS current source instead of a top one is adopted to decrease the tail noise. A current self-adjusted technique without additional external control signals is taken to ensure the VCO starts up in the whole band while keeping the power consumption relatively low. Meanwhile, the phase noise of the VCO at the low frequency （high Cvar） can be reduced by the technique. The circuit is implemented in 0.18 μm CMOS technology. The proposed VCO exhibits low power consumption of 〈1.6 mW at a 1.5 V supply voltage and a tuning range from 11.79 to 12.53 GHz. The measured phase noise at 1 MHz offset from the frequency 11.79 GHz is-104.7 dBc/Hz, and the corresponding FOM is -184.2 dBc/Hz.展开更多
A virtual loop model was built by the transmission analysis with virtual ground method to assist the negative-resistance oscillator design, providing more perspectives on output power and phase-noise optimization. In ...A virtual loop model was built by the transmission analysis with virtual ground method to assist the negative-resistance oscillator design, providing more perspectives on output power and phase-noise optimization. In this work, the virtual loop described the original circuit successfully and the optimizations were effective. A 10 GHz high-efficiency low phase-noise oscillator utilizing an InGaP/GaAs HBT was achieved. The 10.028 GHz oscillator delivered an output power of over 15 dBm with a phase-noise of lower than -107 dBc/Hz at 100 kHz offset. The efficiency of DC to RF transformation was 35 %. The results led to a good oscillator figure of merit of-188 dBc/Hz. The measurement results agreed well with those of the simulations.展开更多
基金Project supported by the Project on the Integration of Industry,Education and Research of Guangdong Province,China(No.2012B090600035)
文摘This paper presents the design and implementation of a current self-adjusted VCO with low power consumption. In the proposed VCO, a bottom PMOS current source instead of a top one is adopted to decrease the tail noise. A current self-adjusted technique without additional external control signals is taken to ensure the VCO starts up in the whole band while keeping the power consumption relatively low. Meanwhile, the phase noise of the VCO at the low frequency （high Cvar） can be reduced by the technique. The circuit is implemented in 0.18 μm CMOS technology. The proposed VCO exhibits low power consumption of 〈1.6 mW at a 1.5 V supply voltage and a tuning range from 11.79 to 12.53 GHz. The measured phase noise at 1 MHz offset from the frequency 11.79 GHz is-104.7 dBc/Hz, and the corresponding FOM is -184.2 dBc/Hz.
文摘A virtual loop model was built by the transmission analysis with virtual ground method to assist the negative-resistance oscillator design, providing more perspectives on output power and phase-noise optimization. In this work, the virtual loop described the original circuit successfully and the optimizations were effective. A 10 GHz high-efficiency low phase-noise oscillator utilizing an InGaP/GaAs HBT was achieved. The 10.028 GHz oscillator delivered an output power of over 15 dBm with a phase-noise of lower than -107 dBc/Hz at 100 kHz offset. The efficiency of DC to RF transformation was 35 %. The results led to a good oscillator figure of merit of-188 dBc/Hz. The measurement results agreed well with those of the simulations.
