A multi-channel, fully differential programmable chip for neural recording application is presented. The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain, eight 4thorde...A multi-channel, fully differential programmable chip for neural recording application is presented. The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain, eight 4thorder Bessel switch capacitor filters, an 8-to-1 analog time-division multiplexer, a fully differential successive approximation register analog-to-digital converter （SAR ADC）, and a serial peripheral interface for communication. The neural recording amplifier presents a programmable gain from 53 dB to 68 dB, a tunable low cut-off frequency from 0.1 Hz to 300 Hz, and 3.77μVrms input-referred noise over a 5 kHz bandwidth. The SAR ADC digitizes signals at maximum sampling rate of 20 μS/s per channel and achieves an ENOB of 7.4. The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process. We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.展开更多
A design for a CMOS frontend integrated circuit （chip） for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplif...A design for a CMOS frontend integrated circuit （chip） for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplifier （IA） and a cyclic analog-to-digital converter （CADC）. The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a -3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device. A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain. The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μVrms integrated from 1 Hz to 5 kHz. The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s. The measured effective number of bits （ENOB） of the ADC is 8.7 bits. The entire circuit draws 165 to 216 μA current from the supply voltage varied from 1.34 to 3.3 V. The prototype chip is fabricated in the 0.18-μm CMOS process and occupies an area of 1.23 mm2 （including pads）. In-vitro recording was successfully carried out by the proposed frontend chip.展开更多
基金supported by the National Basic Research Program of China(No.2011CB933203)the National Natural Science Foundation of China(Nos.61076023,61178051)the National High Technology Research & Development Program of China(No.2012AA030608)
文摘A multi-channel, fully differential programmable chip for neural recording application is presented. The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain, eight 4thorder Bessel switch capacitor filters, an 8-to-1 analog time-division multiplexer, a fully differential successive approximation register analog-to-digital converter （SAR ADC）, and a serial peripheral interface for communication. The neural recording amplifier presents a programmable gain from 53 dB to 68 dB, a tunable low cut-off frequency from 0.1 Hz to 300 Hz, and 3.77μVrms input-referred noise over a 5 kHz bandwidth. The SAR ADC digitizes signals at maximum sampling rate of 20 μS/s per channel and achieves an ENOB of 7.4. The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process. We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.
基金Project supported by the National Natural Science Foundation of China(Nos.61474107,61372060,61335010,61275200,61178051)the Key Program of the Chinese Academy of Sciences(No.KJZD-EW-L11-01)
文摘A design for a CMOS frontend integrated circuit （chip） for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplifier （IA） and a cyclic analog-to-digital converter （CADC）. The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a -3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device. A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain. The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μVrms integrated from 1 Hz to 5 kHz. The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s. The measured effective number of bits （ENOB） of the ADC is 8.7 bits. The entire circuit draws 165 to 216 μA current from the supply voltage varied from 1.34 to 3.3 V. The prototype chip is fabricated in the 0.18-μm CMOS process and occupies an area of 1.23 mm2 （including pads）. In-vitro recording was successfully carried out by the proposed frontend chip.
