In this work,an idea which applies binary alloy nanocrystal floating gate to nonvolatile memory application was introduced.The relationship between binary alloy’s work function and its composition was discussed theor...In this work,an idea which applies binary alloy nanocrystal floating gate to nonvolatile memory application was introduced.The relationship between binary alloy’s work function and its composition was discussed theoretically.A nanocrystal floating gate structure with NiFe nanocrystals embedded in SiO2 dielectric layers was fabricated by magnetron sputtering.The micro-structure and composition deviation of the prepared NiFe nanocrystals were also investigated by TEM and EDS.展开更多
A novel two-step method is employed, for the first time, to fabricatc nonvolatile memory devices that have metal nanoerystals. First, size-averaged Au nanocrystals are synthesized chemically; second, they are assemble...A novel two-step method is employed, for the first time, to fabricatc nonvolatile memory devices that have metal nanoerystals. First, size-averaged Au nanocrystals are synthesized chemically; second, they are assembled into memory devices by a spin-coating technique at room temperature. This attractive approach makes it possible to tailor the diameter and control the density of nanocrystals individually. In addition, processes at room temperature prevent Au diffusion, which is a main concem for the application of metal nanocrystal-based memory. The experimental results, both the morphology characterization and the electrical measurements, reveal that there is an optimum density of nanocrystal monolayer to balance between long data retention and a large hysteresis memory window. At the same time, density-controllable devices could also feed the preferential emphasis on either memory window or retention time. All these facts confirm the advantages and novelty of our two-step method.展开更多
The combination of capacitance- and current-voltage （CV/IV） measurements is used to analyze trap generation in sili- con-nanocrystal memory devices during Fowler-Nordheim （FN） programming/erasing cycling. CV and I...The combination of capacitance- and current-voltage （CV/IV） measurements is used to analyze trap generation in sili- con-nanocrystal memory devices during Fowler-Nordheim （FN） programming/erasing cycling. CV and IV curves are meas- ured after certain P/E cycles. The flatband voltage （Vro） and the threshold voltage （VtQ are extracted from CV curves by solv- ing one-dimensional Schrtidinger and Poisson equations. Both hole and electron trappings are observed in the tunneling SiO2. They show up in the accumulation and the inversion, respectively. By fitting FN tunneling current, the area densities of cy- cling-induced electron traps in the blocking oxide and in the tunneling oxide are finally determined.展开更多
A method of fabricating Cu nanocrystals embedded in SiO2 dielectric film for nonvolatile memory applications by magnetron sputtering is introduced in this paper. The average size and distribution density of Cu nanocry...A method of fabricating Cu nanocrystals embedded in SiO2 dielectric film for nonvolatile memory applications by magnetron sputtering is introduced in this paper. The average size and distribution density of Cu nanocrystal grains are controlled by adjusting experimental parameters. The relationship between nanocrystal floating gate micro-structure and its charge storage capability is also discussed theoretically.展开更多
Two methods are proposed to fabricate stacked ruthenium （Ru） nanocrystals （NCs）： rapid thermal annealing （RTA） for the whole gate stacks, and RTA before each SiO2 layer deposition. The size and aerial density o...Two methods are proposed to fabricate stacked ruthenium （Ru） nanocrystals （NCs）： rapid thermal annealing （RTA） for the whole gate stacks, and RTA before each SiO2 layer deposition. The size and aerial density of Ru NCs are 2-4 nm and 3 × 10^12 cm^-2 for the former method, compared to 3-7 nm and 2 ×10^12 cm^-2 for the latter. Because of the higher surface trap density and more uniform electron tunneling path between upper and lower Ru NCs, a 5.2 V memory window and 1 V after a period of 10 years are observed in metal oxide semiconductor （MOS） capacitors fabricated by the former method, which are much better than 4.6 V and no window remaining after one year observed in the latter. The former method is compatible with conventional CMOS technology.展开更多
Performance and reliability ofa 2 transistor Si nanocrystal nonvolatile memory （NVM） are investigated. A good performance of the memory cell has been achieved, including a fast program/erase （P/E） speed under low ...Performance and reliability ofa 2 transistor Si nanocrystal nonvolatile memory （NVM） are investigated. A good performance of the memory cell has been achieved, including a fast program/erase （P/E） speed under low voltages, an excellent data retention （maintaining for 10 years） and good endurance with a less threshold voltage shift of less than 10% after 104 P/E cycles. The data show that the device has strong potential for future embedded NVM applications.展开更多
Nonvolatile memories （NVMs） with triple layers of silicon nanocrystals were fabricated with conventional CMOS technology. This paper explores the program/erase performance and reliability of NVMs with three layers o...Nonvolatile memories （NVMs） with triple layers of silicon nanocrystals were fabricated with conventional CMOS technology. This paper explores the program/erase performance and reliability of NVMs with three layers of nanocrystais. The results indicate that the nanocrystals in the triple-layer nanocrystal NVM （NCNVM） are difficult to fully charge during the programming process. The programming speed of the triple-layer NCNVMs is quicker than that of single-layer NCNVMs, which means that the second and third layers of nanocrystals in the triple-layer NCNVM affect the charge of the first layer nanocrystals. Reliability tests show that the memory window has little degradation after 1× 10^4 cycles.展开更多
Based on the capacitive coupling formalism, an analytic model for calculating the drain currents of the quantum-dots floating-gate memory cell is proposed. Using this model, one can calculate numerically the drain cur...Based on the capacitive coupling formalism, an analytic model for calculating the drain currents of the quantum-dots floating-gate memory cell is proposed. Using this model, one can calculate numerically the drain currents of linear, saturation and subthreshold regions of the device with/without charges stored on the floating dots. The read operation process of an n-channel Si quantum-dots floating-gate nano-memory cell is discussed after calculating the drain currents versus the drain to source voltages and control gate voltages in both high and low threshold states respectively.展开更多
The charge storage characteristics of P-channel Ge/Si hetero-nanocrystal based MOSFET memory has been investigated and a logical array has been constructed using this memory cell. In the case of the thickness of tunne...The charge storage characteristics of P-channel Ge/Si hetero-nanocrystal based MOSFET memory has been investigated and a logical array has been constructed using this memory cell. In the case of the thickness of tunneling oxide Tox = 2 nm and the dimensions of Si- and Ge-nanocrystal Dsi = DGe = 5 nm, the retention time of this device can reach ten years(～1 × 108 s) while the programming and erasing time achieve the orders of microsecond and millisecond at the control gate voltage | Vg | = 3 V with respect to N-wells,respectively. Therefore, this novel device, as an excellent nonvolatile memory operating at room temperature,is desired to obtain application in future VLSI.展开更多
The rapid thermal annealing （RTA） nano-crystallization method is widely used in the metal nanocrystal fabrication process. However, the high temperature （usually 600 900 ℃） in the RTA process will worsen the per-...The rapid thermal annealing （RTA） nano-crystallization method is widely used in the metal nanocrystal fabrication process. However, the high temperature （usually 600 900 ℃） in the RTA process will worsen the per- formance and reliability of devices. A novel method has been proposed to grow metal nanocrystal by synchronous in situ nano-crystallization of metal thin film （SINC）, which is able to resolve the problems mentioned above. Com- pared with Ni nanocrystals （NCs） formed by RTA, Ni NCs prepared by SINC can obtain more energy to crystallize, and its crystallization temperature is greatly reduced. A large memory window （2.78 V） was observed for Ni NCs deposited by SINC at 300 ℃. However, the largest window is only 1.26 V for Ni NCs formed by RTA at 600 ℃. A large change （from 0.20 to 4.59 V） of the memory window was observed while the operation voltage increased from 0 to 4-10 V, which is due to an occurrence of strong carrier trapping in Ni NCs. Flat-band voltage shift rapidly increases to its saturation value, which indicates that electron/hole trapping in Ni NCs mainly occurs at the initial stage of the program/erase process. A theoretical model was proposed to characterize the charging and discharging processes.展开更多
The N2-plasma treatment on a HfO2 blocking layer of Au nanocrystal nonvolatile memory without any post annealing is investigated. The electrical characteristics of the MOS capacitor with structure of Al–Ta N/HfO2/Si ...The N2-plasma treatment on a HfO2 blocking layer of Au nanocrystal nonvolatile memory without any post annealing is investigated. The electrical characteristics of the MOS capacitor with structure of Al–Ta N/HfO2/Si O2/p-Si are also characterized. After N2-plasma treatment, the nitrogen atoms are incorporated into HfO2 film and may passivate the oxygen vacancy states. The surface roughness of HfO2 film can also be reduced. Those improvements of HfO2 film lead to a smaller hysteresis and lower leakage current density of the MOS capacitor. The N2-plasma is introduced into Au nanocrystal（NC） nonvolatile memory to treat the HfO2 blocking layer. For the N2-plasma treated device, it shows a better retention characteristic and is twice as large in the memory window than that for the no N2-plasma treated device. It can be concluded that the N2-plasma treatment method can be applied to future nonvolatile memory applications.展开更多
Non-volatile memory based on TiN nanocrystal （TiN-NC） charge storage nodes embedded in SiO2 has been fabricated and its electrical properties have been measured. It was found that the density and size distribution o...Non-volatile memory based on TiN nanocrystal （TiN-NC） charge storage nodes embedded in SiO2 has been fabricated and its electrical properties have been measured. It was found that the density and size distribution of TiN-NCs can be controlled by annealing temperature. The formation of well separated crystalline TiN nano-dots with an average size of 5 nm is confirmed by transmission electron microscopy and x-ray diffraction, x-ray photoelectron spectroscopy confirms the existence of a transition layer of TiNxOy/SiON oxide between TiN-NC and SiO2, which reduces the barrier height of tunnel oxide and thereby enhances programming/erasing speed. The memory device shows a memory window of 2.5V and an endurance cycle throughout 10^5. Its charging mechanism, which is interpreted from the analysis of programming speed （dVth/dt） and the gate leakage versus voltage characteristics （Ig vs Vg）, has been explained by direct tunnelling for tunnel oxide and Fowler Nordheim tunnelling for control oxide at programming voltages lower than 9V, and by Fowler-Nordheim tunnelling for both the oxides at programming voltages higher than 9V.展开更多
文摘In this work,an idea which applies binary alloy nanocrystal floating gate to nonvolatile memory application was introduced.The relationship between binary alloy’s work function and its composition was discussed theoretically.A nanocrystal floating gate structure with NiFe nanocrystals embedded in SiO2 dielectric layers was fabricated by magnetron sputtering.The micro-structure and composition deviation of the prepared NiFe nanocrystals were also investigated by TEM and EDS.
文摘A novel two-step method is employed, for the first time, to fabricatc nonvolatile memory devices that have metal nanoerystals. First, size-averaged Au nanocrystals are synthesized chemically; second, they are assembled into memory devices by a spin-coating technique at room temperature. This attractive approach makes it possible to tailor the diameter and control the density of nanocrystals individually. In addition, processes at room temperature prevent Au diffusion, which is a main concem for the application of metal nanocrystal-based memory. The experimental results, both the morphology characterization and the electrical measurements, reveal that there is an optimum density of nanocrystal monolayer to balance between long data retention and a large hysteresis memory window. At the same time, density-controllable devices could also feed the preferential emphasis on either memory window or retention time. All these facts confirm the advantages and novelty of our two-step method.
基金supported by the National Basic Research Program of China ("973" Program) (Grant No. 2010CB934200)the National Natural Science Foundation of China (Grant No. 60825403)the Hi-Tech Research and Development Program of China ("863" Program) ( Grant No. 2008AA031403)
文摘The combination of capacitance- and current-voltage （CV/IV） measurements is used to analyze trap generation in sili- con-nanocrystal memory devices during Fowler-Nordheim （FN） programming/erasing cycling. CV and IV curves are meas- ured after certain P/E cycles. The flatband voltage （Vro） and the threshold voltage （VtQ are extracted from CV curves by solv- ing one-dimensional Schrtidinger and Poisson equations. Both hole and electron trappings are observed in the tunneling SiO2. They show up in the accumulation and the inversion, respectively. By fitting FN tunneling current, the area densities of cy- cling-induced electron traps in the blocking oxide and in the tunneling oxide are finally determined.
文摘A method of fabricating Cu nanocrystals embedded in SiO2 dielectric film for nonvolatile memory applications by magnetron sputtering is introduced in this paper. The average size and distribution density of Cu nanocrystal grains are controlled by adjusting experimental parameters. The relationship between nanocrystal floating gate micro-structure and its charge storage capability is also discussed theoretically.
基金Project supported by the State Key Development Program for Basic Research of China(No.2006CB302702)the National Hi-TechResearch and Development Program of China(No.2008AA031403)
文摘Two methods are proposed to fabricate stacked ruthenium （Ru） nanocrystals （NCs）： rapid thermal annealing （RTA） for the whole gate stacks, and RTA before each SiO2 layer deposition. The size and aerial density of Ru NCs are 2-4 nm and 3 × 10^12 cm^-2 for the former method, compared to 3-7 nm and 2 ×10^12 cm^-2 for the latter. Because of the higher surface trap density and more uniform electron tunneling path between upper and lower Ru NCs, a 5.2 V memory window and 1 V after a period of 10 years are observed in metal oxide semiconductor （MOS） capacitors fabricated by the former method, which are much better than 4.6 V and no window remaining after one year observed in the latter. The former method is compatible with conventional CMOS technology.
基金Project supported by the State Key Development Program for Basic Research of China(Nos.2010CB934200 2011CBA00602)the National Natural Science Foundation of China(No.60825403)+2 种基金the National Key Project(Nos.2009ZX-02302-004,2009ZX-02302-005-1)the National Hi-Tech Research and Development Program of China(No.2008AA031403)the Director's Fund of IMECAS
文摘Performance and reliability ofa 2 transistor Si nanocrystal nonvolatile memory （NVM） are investigated. A good performance of the memory cell has been achieved, including a fast program/erase （P/E） speed under low voltages, an excellent data retention （maintaining for 10 years） and good endurance with a less threshold voltage shift of less than 10% after 104 P/E cycles. The data show that the device has strong potential for future embedded NVM applications.
基金Supported by the Basic Research Foundation of Tsinghua National Laboratory for Information Science and Technology (TNList)
文摘Nonvolatile memories （NVMs） with triple layers of silicon nanocrystals were fabricated with conventional CMOS technology. This paper explores the program/erase performance and reliability of NVMs with three layers of nanocrystais. The results indicate that the nanocrystals in the triple-layer nanocrystal NVM （NCNVM） are difficult to fully charge during the programming process. The programming speed of the triple-layer NCNVMs is quicker than that of single-layer NCNVMs, which means that the second and third layers of nanocrystals in the triple-layer NCNVM affect the charge of the first layer nanocrystals. Reliability tests show that the memory window has little degradation after 1× 10^4 cycles.
基金Foundation for Key Youth Teachers from Hunan Province(521105237)
文摘Based on the capacitive coupling formalism, an analytic model for calculating the drain currents of the quantum-dots floating-gate memory cell is proposed. Using this model, one can calculate numerically the drain currents of linear, saturation and subthreshold regions of the device with/without charges stored on the floating dots. The read operation process of an n-channel Si quantum-dots floating-gate nano-memory cell is discussed after calculating the drain currents versus the drain to source voltages and control gate voltages in both high and low threshold states respectively.
文摘The charge storage characteristics of P-channel Ge/Si hetero-nanocrystal based MOSFET memory has been investigated and a logical array has been constructed using this memory cell. In the case of the thickness of tunneling oxide Tox = 2 nm and the dimensions of Si- and Ge-nanocrystal Dsi = DGe = 5 nm, the retention time of this device can reach ten years(～1 × 108 s) while the programming and erasing time achieve the orders of microsecond and millisecond at the control gate voltage | Vg | = 3 V with respect to N-wells,respectively. Therefore, this novel device, as an excellent nonvolatile memory operating at room temperature,is desired to obtain application in future VLSI.
基金Project supported by the National Natural Science Foundation of China(No.61076055)the Open Project Program of Surface Physics Laboratory(National Key Laboratory)of Fudan University(No.KL2011_04)
文摘The rapid thermal annealing （RTA） nano-crystallization method is widely used in the metal nanocrystal fabrication process. However, the high temperature （usually 600 900 ℃） in the RTA process will worsen the per- formance and reliability of devices. A novel method has been proposed to grow metal nanocrystal by synchronous in situ nano-crystallization of metal thin film （SINC）, which is able to resolve the problems mentioned above. Com- pared with Ni nanocrystals （NCs） formed by RTA, Ni NCs prepared by SINC can obtain more energy to crystallize, and its crystallization temperature is greatly reduced. A large memory window （2.78 V） was observed for Ni NCs deposited by SINC at 300 ℃. However, the largest window is only 1.26 V for Ni NCs formed by RTA at 600 ℃. A large change （from 0.20 to 4.59 V） of the memory window was observed while the operation voltage increased from 0 to 4-10 V, which is due to an occurrence of strong carrier trapping in Ni NCs. Flat-band voltage shift rapidly increases to its saturation value, which indicates that electron/hole trapping in Ni NCs mainly occurs at the initial stage of the program/erase process. A theoretical model was proposed to characterize the charging and discharging processes.
基金supported by the High Level Talent Project of Xiamen University of Technology,China(Grant Nos.YKJ16012R and YKJ16016R)the National Natural Science Foundation of China(Grant No.51702271)
文摘The N2-plasma treatment on a HfO2 blocking layer of Au nanocrystal nonvolatile memory without any post annealing is investigated. The electrical characteristics of the MOS capacitor with structure of Al–Ta N/HfO2/Si O2/p-Si are also characterized. After N2-plasma treatment, the nitrogen atoms are incorporated into HfO2 film and may passivate the oxygen vacancy states. The surface roughness of HfO2 film can also be reduced. Those improvements of HfO2 film lead to a smaller hysteresis and lower leakage current density of the MOS capacitor. The N2-plasma is introduced into Au nanocrystal（NC） nonvolatile memory to treat the HfO2 blocking layer. For the N2-plasma treated device, it shows a better retention characteristic and is twice as large in the memory window than that for the no N2-plasma treated device. It can be concluded that the N2-plasma treatment method can be applied to future nonvolatile memory applications.
文摘Non-volatile memory based on TiN nanocrystal （TiN-NC） charge storage nodes embedded in SiO2 has been fabricated and its electrical properties have been measured. It was found that the density and size distribution of TiN-NCs can be controlled by annealing temperature. The formation of well separated crystalline TiN nano-dots with an average size of 5 nm is confirmed by transmission electron microscopy and x-ray diffraction, x-ray photoelectron spectroscopy confirms the existence of a transition layer of TiNxOy/SiON oxide between TiN-NC and SiO2, which reduces the barrier height of tunnel oxide and thereby enhances programming/erasing speed. The memory device shows a memory window of 2.5V and an endurance cycle throughout 10^5. Its charging mechanism, which is interpreted from the analysis of programming speed （dVth/dt） and the gate leakage versus voltage characteristics （Ig vs Vg）, has been explained by direct tunnelling for tunnel oxide and Fowler Nordheim tunnelling for control oxide at programming voltages lower than 9V, and by Fowler-Nordheim tunnelling for both the oxides at programming voltages higher than 9V.
