Multi-core architectures are widely used to in time-to-market and power consumption of the chips enhance the microprocessor performance within a limited increase Toward the application of high-density data signal pro...Multi-core architectures are widely used to in time-to-market and power consumption of the chips enhance the microprocessor performance within a limited increase Toward the application of high-density data signal processing, this paper presents a novel heterogeneous multi-core architecture digital signal processor （DSP）, YHFT-QDSP, with one RISC CPU core and 4 VLIW DSP cores. By three kinds of interconnection, YHFT-QDSP provides high efficiency message communication for inner-chip RISC core and DSP cores, inner-chip and inter-chip DSP cores. A parallel programming platform is specifically developed for the heterogeneous nmlti-core architecture of YHFT-QDSP. This parallel programming environment provides a parallel support library and a friendly interface between high level application softwares and multi- core DSP. The 130 nm CMOS custom chip design results benchmarks show that the interconnection structure of in a high speed and moderate power design. The results of typical YHFT-QDSP is much better than other related structures and achieves better speedup when using the interconnection facilities in combing methods. YHFT-QDSP has been signed off and manufactured presently. The future applications of the multi-core chip could be found in 3G wireless base station, high performance radar, industrial applications, and so on.展开更多
以多核数字信号处理器(Digital Signal Processor,DSP)作为计算节点的多核DSP集群系统成为一大发展趋势。当前阶段,由于多核DSP内核硬件资源利用不充分与访存带宽限制,峰值性能与实际性能间存在鸿沟。基于C66x内核丰富的指令集架构以及...以多核数字信号处理器(Digital Signal Processor,DSP)作为计算节点的多核DSP集群系统成为一大发展趋势。当前阶段,由于多核DSP内核硬件资源利用不充分与访存带宽限制,峰值性能与实际性能间存在鸿沟。基于C66x内核丰富的指令集架构以及运算指令编排原则,结合编译器提供的汇编信息,设计并优化了QR分解算法,在充分挖掘DSP单核性能极致的同时减少了矩阵分解的计算时间。根据掌握的优化技术,设计并实现基于多核DSP集群系统的大规模并行QR分解模型,并在分布式计算框架上完成了分解任务。分析结果表明,优化后的QR分解计算效率以及C66x单核硬件资源使用率均提升了二十余倍,随着待分解矩阵规模的成倍增加,多核DSP集群相比于单核的计算性能提升也愈加明显。展开更多
基金supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China under Grant No.2009ZX01034-001-001-006the National High Technology Research and Development 863 Program of China under Grant No.2007AA01Z108the Program for Changjiang Scholars and Innovative Research Team in Universities of China under Grant No.IRT0614.
文摘Multi-core architectures are widely used to in time-to-market and power consumption of the chips enhance the microprocessor performance within a limited increase Toward the application of high-density data signal processing, this paper presents a novel heterogeneous multi-core architecture digital signal processor （DSP）, YHFT-QDSP, with one RISC CPU core and 4 VLIW DSP cores. By three kinds of interconnection, YHFT-QDSP provides high efficiency message communication for inner-chip RISC core and DSP cores, inner-chip and inter-chip DSP cores. A parallel programming platform is specifically developed for the heterogeneous nmlti-core architecture of YHFT-QDSP. This parallel programming environment provides a parallel support library and a friendly interface between high level application softwares and multi- core DSP. The 130 nm CMOS custom chip design results benchmarks show that the interconnection structure of in a high speed and moderate power design. The results of typical YHFT-QDSP is much better than other related structures and achieves better speedup when using the interconnection facilities in combing methods. YHFT-QDSP has been signed off and manufactured presently. The future applications of the multi-core chip could be found in 3G wireless base station, high performance radar, industrial applications, and so on.
文摘以多核数字信号处理器(Digital Signal Processor,DSP)作为计算节点的多核DSP集群系统成为一大发展趋势。当前阶段,由于多核DSP内核硬件资源利用不充分与访存带宽限制,峰值性能与实际性能间存在鸿沟。基于C66x内核丰富的指令集架构以及运算指令编排原则,结合编译器提供的汇编信息,设计并优化了QR分解算法,在充分挖掘DSP单核性能极致的同时减少了矩阵分解的计算时间。根据掌握的优化技术,设计并实现基于多核DSP集群系统的大规模并行QR分解模型,并在分布式计算框架上完成了分解任务。分析结果表明,优化后的QR分解计算效率以及C66x单核硬件资源使用率均提升了二十余倍,随着待分解矩阵规模的成倍增加,多核DSP集群相比于单核的计算性能提升也愈加明显。
