This work described the electrical characteristics of a kind of amorphous Gd2O3-doped HfO2 insulator for high-k metal-oxide-semiconductor(MOS) capacitors.Compared with pure HfO2,the doped HfO2 with an optimum concentr...This work described the electrical characteristics of a kind of amorphous Gd2O3-doped HfO2 insulator for high-k metal-oxide-semiconductor(MOS) capacitors.Compared with pure HfO2,the doped HfO2 with an optimum concentration of Gd2O3 as MOS gate dielectric exhibited a lower leakage current,thinner effective oxide thickness and less fixed oxide charges density.The result indicated that Gd2O3 doping power of 60 W exhibited the best electrical characteristics,maximum capacitance,lowest leakage current of 9.35079...展开更多
To build an accurate electric model for through-silicon vias （TSVs） in 3D integrated circuits （ICs）, a resistance and capacitance （RC） circuit model and related efficient extraction technique are proposed. The c...To build an accurate electric model for through-silicon vias （TSVs） in 3D integrated circuits （ICs）, a resistance and capacitance （RC） circuit model and related efficient extraction technique are proposed. The circuit model takes both semiconductor and electrostatic effects into account, and is valid for low and medium signal frequencies. The electrostatic capacitances are extracted with a floating random walk based algorithm, and are then combined with the voltage-dependent semiconductor capacitances to form the equivalent circuit. Compared with the method used in Synopsys＇s Sdevice, which completely simulates the electro/semiconductor effects, the proposed method is more efficient and is able to handle the general TSV layout as well. For several TSV structures, the experimental results validate the accuracy of the proposed method for the frequency range from l0 kHz to 1 GHz. The proposed method demonstrated 47× speedup over the Sdevice for the largest 9-TSV case.展开更多
This paper proposes an efficient PSP-based model for cross-coupled metal-oxide-semiconductor field-effect transistors(MOSFETs) with optimized layout in the voltage controlled oscillator(VCO).The model employs a PSP ch...This paper proposes an efficient PSP-based model for cross-coupled metal-oxide-semiconductor field-effect transistors(MOSFETs) with optimized layout in the voltage controlled oscillator(VCO).The model employs a PSP charge model to characterize the bias-dependent extrinsic capacitance instead of numerical functions with strong non-linearity.The simulation convergence is greatly improved by this method.An original scheme is developed to extract the parameters of the PSP charge model based on S-parameters measurement.The interconnection parasitics of the cross-coupled MOSFETs are modeled based on vector fitting.The model is verified with an LC VCO design,and exhibits excellent convergence during simulation.The results show improvements as high as 60.5% and 61.8% in simulation efficiency and accuracy,respectively,indicating that the proposed model better characterizes optimized cross-coupled MOSFETs in advanced radio frequency(RF) circuit design.展开更多
A GaAs metal-oxide-semiconductor （MOS） capacitor with HfO2 as gate dielectric and silicon nitride （SiNx） as the interlayer （IL） is fabricated. Experimental results show that the sample with the SiNx IL has an im...A GaAs metal-oxide-semiconductor （MOS） capacitor with HfO2 as gate dielectric and silicon nitride （SiNx） as the interlayer （IL） is fabricated. Experimental results show that the sample with the SiNx IL has an improved capacitance- voltage characteristic, lower leakage current density （0.785 × 10^-6 Alcm^2 at Vfo ＋ 1 V） and lower interface-state density （2.9 × 10^12 eV^-1 ·cm^-2） compared with other samples with N2- or NH3-plasma pretreatment. The influences of post- deposition annealing temperature on electrical properties are also investigated for the samples with SiNx IL. The sample annealed at 600 ℃ exhibits better electrical properties than that annealed at 500 ℃, which is attributed to the suppression of native oxides, as confirmed by XPS analyses.展开更多
This study proposes a new generation of floating gate transistors(FGT)with a novel built-in security feature.The new device has applications in guarding the IC chips against the current reverse engineering techniques,...This study proposes a new generation of floating gate transistors(FGT)with a novel built-in security feature.The new device has applications in guarding the IC chips against the current reverse engineering techniques,including scanning capacitance microscopy(SCM).The SCM measures the change in the C–V characteristic of the device as a result of placing a minute amount of charge on the floating gate,even in nano-meter scales.The proposed design only adds a simple processing step to the conventional FGT by adding an oppositely doped implanted layer to the substrate.This new structure was first analyzed theoretically and then a two-dimensional model was extracted to represent its C–V characteristic.Furthermore,this model was verified with a simulation.In addition,the C–V characteristics relevant to the SCM measurement of both conventional and the new designed FGT were compared to discuss the effectiveness of the added layer in masking the state of the transistor.The effect of change in doping concentration of the implanted layer on the C–V characteristics was also investigated.Finally,the feasibility of the proposed design was examined by comparing its I–V characteristics with the traditional FGT.展开更多
基金supported by the National Key Scientific Research Projects (50932001)
文摘This work described the electrical characteristics of a kind of amorphous Gd2O3-doped HfO2 insulator for high-k metal-oxide-semiconductor(MOS) capacitors.Compared with pure HfO2,the doped HfO2 with an optimum concentration of Gd2O3 as MOS gate dielectric exhibited a lower leakage current,thinner effective oxide thickness and less fixed oxide charges density.The result indicated that Gd2O3 doping power of 60 W exhibited the best electrical characteristics,maximum capacitance,lowest leakage current of 9.35079...
基金supported by the National Natural Science Foundation of China(No.61422402)the Tsinghua University Initiative Scientific Research Program
文摘To build an accurate electric model for through-silicon vias （TSVs） in 3D integrated circuits （ICs）, a resistance and capacitance （RC） circuit model and related efficient extraction technique are proposed. The circuit model takes both semiconductor and electrostatic effects into account, and is valid for low and medium signal frequencies. The electrostatic capacitances are extracted with a floating random walk based algorithm, and are then combined with the voltage-dependent semiconductor capacitances to form the equivalent circuit. Compared with the method used in Synopsys＇s Sdevice, which completely simulates the electro/semiconductor effects, the proposed method is more efficient and is able to handle the general TSV layout as well. For several TSV structures, the experimental results validate the accuracy of the proposed method for the frequency range from l0 kHz to 1 GHz. The proposed method demonstrated 47× speedup over the Sdevice for the largest 9-TSV case.
基金Project supported by the National Basic Research Program (973) of China (No. 2010CB327403)the National Natural Science Foundation of China (Nos. 61001066 and 61102027)
文摘This paper proposes an efficient PSP-based model for cross-coupled metal-oxide-semiconductor field-effect transistors(MOSFETs) with optimized layout in the voltage controlled oscillator(VCO).The model employs a PSP charge model to characterize the bias-dependent extrinsic capacitance instead of numerical functions with strong non-linearity.The simulation convergence is greatly improved by this method.An original scheme is developed to extract the parameters of the PSP charge model based on S-parameters measurement.The interconnection parasitics of the cross-coupled MOSFETs are modeled based on vector fitting.The model is verified with an LC VCO design,and exhibits excellent convergence during simulation.The results show improvements as high as 60.5% and 61.8% in simulation efficiency and accuracy,respectively,indicating that the proposed model better characterizes optimized cross-coupled MOSFETs in advanced radio frequency(RF) circuit design.
基金supported by the National Natural Science Foundation of China (Grant No. 61176100)
文摘A GaAs metal-oxide-semiconductor （MOS） capacitor with HfO2 as gate dielectric and silicon nitride （SiNx） as the interlayer （IL） is fabricated. Experimental results show that the sample with the SiNx IL has an improved capacitance- voltage characteristic, lower leakage current density （0.785 × 10^-6 Alcm^2 at Vfo ＋ 1 V） and lower interface-state density （2.9 × 10^12 eV^-1 ·cm^-2） compared with other samples with N2- or NH3-plasma pretreatment. The influences of post- deposition annealing temperature on electrical properties are also investigated for the samples with SiNx IL. The sample annealed at 600 ℃ exhibits better electrical properties than that annealed at 500 ℃, which is attributed to the suppression of native oxides, as confirmed by XPS analyses.
文摘This study proposes a new generation of floating gate transistors(FGT)with a novel built-in security feature.The new device has applications in guarding the IC chips against the current reverse engineering techniques,including scanning capacitance microscopy(SCM).The SCM measures the change in the C–V characteristic of the device as a result of placing a minute amount of charge on the floating gate,even in nano-meter scales.The proposed design only adds a simple processing step to the conventional FGT by adding an oppositely doped implanted layer to the substrate.This new structure was first analyzed theoretically and then a two-dimensional model was extracted to represent its C–V characteristic.Furthermore,this model was verified with a simulation.In addition,the C–V characteristics relevant to the SCM measurement of both conventional and the new designed FGT were compared to discuss the effectiveness of the added layer in masking the state of the transistor.The effect of change in doping concentration of the implanted layer on the C–V characteristics was also investigated.Finally,the feasibility of the proposed design was examined by comparing its I–V characteristics with the traditional FGT.
