We present a novel standard convolutional symbols generator(SCSG)block for a multi-parameter reconfigurable Viterbi decoder to optimize resource consumption and adaption of multiple parameters.The SCSG block generates...We present a novel standard convolutional symbols generator(SCSG)block for a multi-parameter reconfigurable Viterbi decoder to optimize resource consumption and adaption of multiple parameters.The SCSG block generates all the states and calculates all the possible standard convolutional symbols corresponding to the states using an iterative approach.The architecture of the Viterbi decoder based on the SCSG reduces resource consumption for recalculating the branch metrics and rearranging the correspondence between branch metrics and transition paths.The proposed architecture supports constraint lengths from 3 to 9,code rates of 1/2,1/3,and 1/4,and fully optional polynomials.The proposed Viterbi decoder has been implemented on the Xilinx XC7VX485T device with a high throughput of about 200 Mbps and a low resource consumption of 162k logic gates.展开更多
基金Project supported by the Natural Science Foundation of Jiangsu Province,China(No.BK20130156)the Summit of the Six Top Talents Program of Jiangsu Province,China(No.2013-DZXX-027)+1 种基金the Fundamental Research Funds for the Central Universities,China(No.JUSRP51510)the Graduate Student Innovation Program for Universities of Jiangsu Province,China(Nos.KYLX15_1192,KYLX16_0776,and SJLX16_0500)
文摘We present a novel standard convolutional symbols generator(SCSG)block for a multi-parameter reconfigurable Viterbi decoder to optimize resource consumption and adaption of multiple parameters.The SCSG block generates all the states and calculates all the possible standard convolutional symbols corresponding to the states using an iterative approach.The architecture of the Viterbi decoder based on the SCSG reduces resource consumption for recalculating the branch metrics and rearranging the correspondence between branch metrics and transition paths.The proposed architecture supports constraint lengths from 3 to 9,code rates of 1/2,1/3,and 1/4,and fully optional polynomials.The proposed Viterbi decoder has been implemented on the Xilinx XC7VX485T device with a high throughput of about 200 Mbps and a low resource consumption of 162k logic gates.
文摘为了解决高速数字接收机中混频数据处理能力有限的问题,设计了基于八分圆周矢量旋转(OCVR)的高速数字正交混频器.该混频器仅通过简单二进制补码运算器和移位加法器即可实现,且不需要进行迭代运算.分析比较了常规的基于ROM架构、基于直接坐标旋转数字计算机(CORDIC)架构以及基于OCVR架构的混频器,结果显示基于OCVR的混频器拥有更高的数据吞吐量、更低的硬件资源消耗以及混频噪声小等特点.根据OCVR特性设计了武汉电离层斜向返回探测系统(WIOBSS)的中频(IF)数字接收机,该系统可以获取实时的宽带扫频后向散射电离图.实验证明该系统的探测覆盖范围已经延伸至3 000 km.
