The design of a router in a network-on-chip （NoC） system has an important impact on some perfor- mance criteria. In this paper, we propose a low overhead load balancing router （LOLBR） for 2D mesh NoC to enhance ro...The design of a router in a network-on-chip （NoC） system has an important impact on some perfor- mance criteria. In this paper, we propose a low overhead load balancing router （LOLBR） for 2D mesh NoC to enhance routing performance criteria with low hardware overhead. The proposed LOLBR employs a balance tog- gle identifier to control the initial routing direction of X or Y for flit injection. The simplified demultiplexers and multiplexers are used to handle output ports allocation and contention, which provide a guarantee of deadlock avoidance. Simulation results show that the proposed LOLBR yields an improvement of routing performance over the reported routing schemes in average packet latency by 26.5%. The layout area and power consumption of the network compared with the reported routing schemes are 15.3% and 11.6% less respectively.展开更多
基金Project supported by the National Natural Science Foundation of China(Nos.61474087,61322405,61376039)
文摘The design of a router in a network-on-chip （NoC） system has an important impact on some perfor- mance criteria. In this paper, we propose a low overhead load balancing router （LOLBR） for 2D mesh NoC to enhance routing performance criteria with low hardware overhead. The proposed LOLBR employs a balance tog- gle identifier to control the initial routing direction of X or Y for flit injection. The simplified demultiplexers and multiplexers are used to handle output ports allocation and contention, which provide a guarantee of deadlock avoidance. Simulation results show that the proposed LOLBR yields an improvement of routing performance over the reported routing schemes in average packet latency by 26.5%. The layout area and power consumption of the network compared with the reported routing schemes are 15.3% and 11.6% less respectively.
