A number of conventional interpolation techniques have been proposed. However, it seems that there do not exist good criteria for the design of optimal linear interpolators. Also, such an interpolator can hardly provi...A number of conventional interpolation techniques have been proposed. However, it seems that there do not exist good criteria for the design of optimal linear interpolators. Also, such an interpolator can hardly provide a satisfactory solution for interpolating noisy images. In this paper, the novelty of this research is that a universal approach is proposed to design an image interpolator with any one image smoothing filter, thereby not only interpolating a down-sampled image but also preserving the characteristics of the performing filtering.展开更多
This paper presents the design considerations and implementation of an area-efficient interpolator suitable for a delta-sigma D/A converter. In an effort to reduce the area and design complexity, a method for designin...This paper presents the design considerations and implementation of an area-efficient interpolator suitable for a delta-sigma D/A converter. In an effort to reduce the area and design complexity, a method for designing an FIR filter as a tapped cascaded interconnection of identical subfilters is modified. The proposed subfilter structure further minimizes the arithmetic number. Experimental results show that the proposed interpolator achieves the design specification,exhibiting high performance and hardware efficiency,and also has good noise rejection capability. The interpolation filter can be applied to a delta-sigma DAC and is fully functional.展开更多
A multi-standard compatible clock and data recovery circuit （CDR） with a programmable equalizer and wide tracking range is presented. Considering the jitter performance, tracking range and chip area, the CDR employs...A multi-standard compatible clock and data recovery circuit （CDR） with a programmable equalizer and wide tracking range is presented. Considering the jitter performance, tracking range and chip area, the CDR employs a first-order digital loop filter, two 6-bit DACs and high linearity phase interpolators to achieve high phase resolution and low area. Meanwhile the tracking range is greater than 4-2200 ppm, making this proposed CDR suitable for the embedded clock serial links. A test chip was fabricated in the 55 nm CMOS process. The measurements show that the test chip can achieve BER 〈 10^-12 and meet the jitter tolerance specification. The test chip occupies 0.19 mma with a 0.0486 mm^2 CDR core, which only consumes 30 mW from a 1.2 V supply at 5 Gb/s.展开更多
A wide-range tracking technique for clock and data recovery(CDR) circuit is presented. Compared to the traditional technique, a digital CDR controller with calibration is adopted to extend the tracking range. Because ...A wide-range tracking technique for clock and data recovery(CDR) circuit is presented. Compared to the traditional technique, a digital CDR controller with calibration is adopted to extend the tracking range. Because of the use of digital circuits in the design, CDR is not sensitive to process and power supply variations. To verify the technique, the whole CDR circuit is implemented using 65-nm CMOS technology. Measurements show that the tracking range of CDR is greater than ±6×10-3 at 5 Gb/s. The receiver has good jitter tolerance performance and achieves a bit error rate of <10–12. The re-timed and re-multiplexed serial data has a root-mean-square jitter of 6.7 ps.展开更多
文摘A number of conventional interpolation techniques have been proposed. However, it seems that there do not exist good criteria for the design of optimal linear interpolators. Also, such an interpolator can hardly provide a satisfactory solution for interpolating noisy images. In this paper, the novelty of this research is that a universal approach is proposed to design an image interpolator with any one image smoothing filter, thereby not only interpolating a down-sampled image but also preserving the characteristics of the performing filtering.
文摘This paper presents the design considerations and implementation of an area-efficient interpolator suitable for a delta-sigma D/A converter. In an effort to reduce the area and design complexity, a method for designing an FIR filter as a tapped cascaded interconnection of identical subfilters is modified. The proposed subfilter structure further minimizes the arithmetic number. Experimental results show that the proposed interpolator achieves the design specification,exhibiting high performance and hardware efficiency,and also has good noise rejection capability. The interpolation filter can be applied to a delta-sigma DAC and is fully functional.
文摘针对传统的Mash结构由于各级失配导致信噪比低的问题,本文采用一阶相位累加器来实现传统的sigma-delta(Σ-Δ)架构,并将其采用硬件描述语言来实现,这样整个系统均在数字域实现,从根本上解决了各级间的失配问题.在插值滤波器的设计上,使用优化了的半带滤波器结构和级联积分梳状滤波器,节省了硬件资源.电路采用的是Magnachip 180nm 1P4M标准CMOS工艺,芯片面积只有0.2025mm^2(0.45×0.45),实测芯片得到的信噪失真比(SNDR)达到90d B.
基金Project supported by the National High Technology Research and Development Program of China(No.2011AA010403)the National Natural Science Foundation of China(No.61474134)the National Science and Technology Major Project(No.2014ZX02302002)
文摘A multi-standard compatible clock and data recovery circuit （CDR） with a programmable equalizer and wide tracking range is presented. Considering the jitter performance, tracking range and chip area, the CDR employs a first-order digital loop filter, two 6-bit DACs and high linearity phase interpolators to achieve high phase resolution and low area. Meanwhile the tracking range is greater than 4-2200 ppm, making this proposed CDR suitable for the embedded clock serial links. A test chip was fabricated in the 55 nm CMOS process. The measurements show that the test chip can achieve BER 〈 10^-12 and meet the jitter tolerance specification. The test chip occupies 0.19 mma with a 0.0486 mm^2 CDR core, which only consumes 30 mW from a 1.2 V supply at 5 Gb/s.
基金Project supported by the National High-Tech R&D Program(863)of China(No.2011AA010403)the National Natural Science Foundation of China(No.61474134)
文摘A wide-range tracking technique for clock and data recovery(CDR) circuit is presented. Compared to the traditional technique, a digital CDR controller with calibration is adopted to extend the tracking range. Because of the use of digital circuits in the design, CDR is not sensitive to process and power supply variations. To verify the technique, the whole CDR circuit is implemented using 65-nm CMOS technology. Measurements show that the tracking range of CDR is greater than ±6×10-3 at 5 Gb/s. The receiver has good jitter tolerance performance and achieves a bit error rate of <10–12. The re-timed and re-multiplexed serial data has a root-mean-square jitter of 6.7 ps.
