Interconnections in microelectronic packaging are not only the physical carrier to realize the function of electronic circuits,but also the weak spots in reliability tests.Most of failures in power devices are caused ...Interconnections in microelectronic packaging are not only the physical carrier to realize the function of electronic circuits,but also the weak spots in reliability tests.Most of failures in power devices are caused by the malfunction of interconnections,including failure of bonding wire as well as cracks of solder layer.In fact,the interconnection failure of power devices is the result of a combination of factors such as electricity,temperature,and force.It is significant to investigate the failure mechanisms of various factors for the failure analysis of interconnections in power devices.This paper reviews the main failure modes of bonding wire and solder layer in the interconnection structure of power devices,and its failure mechanism.Then the reliability test method and failure analysis techniques of interconnection in power device are introduced.These methods are of great significance to the reliability analysis and life prediction of power devices.展开更多
随着集成电路技术快速发展,芯片的集成度和密度越来越大,体积和功耗越来越小,IC领域提出了一种新型的超摩尔定律的芯片设计思路——系统级封装(System in Package,SiP)。要在有限的芯片管脚下完成对整个SiP电路系统的测试变得极具挑战,...随着集成电路技术快速发展,芯片的集成度和密度越来越大,体积和功耗越来越小,IC领域提出了一种新型的超摩尔定律的芯片设计思路——系统级封装(System in Package,SiP)。要在有限的芯片管脚下完成对整个SiP电路系统的测试变得极具挑战,急需寻求一种新的测试方法。为此,文中提出了一种基于边界扫描测试方法,在严格遵循紧凑性和完备性的指标下,通过对现有自适应算法中快速生成测试矩阵算法的优化,完成SiP芯片的互连测试。对比分析优化前后各算法的混淆率和紧凑性指标,验证了使用低权值的等权值算法能有效地提高测试的性能。测试的仿真结果表明,基于边界扫描测试的低权值的等权值算法可以满足SiP的测试需求。展开更多
基金supported by the National Natural Science Foundation of China(Grant No.61904127 and 62004144)Guangdong Basic and Applied Basic Research Foundation(Grant No.2021A1515010651)+2 种基金Fundamental Research Funds for the Central Universities(Grant No.202401002,203134004,20212VA100 and 2021VB006)Hubei Provincial Natural Science Foundation of China(Grant No.2020CFA032)National Key R&D Program of China(Grant No.2019YFB1704600)。
文摘Interconnections in microelectronic packaging are not only the physical carrier to realize the function of electronic circuits,but also the weak spots in reliability tests.Most of failures in power devices are caused by the malfunction of interconnections,including failure of bonding wire as well as cracks of solder layer.In fact,the interconnection failure of power devices is the result of a combination of factors such as electricity,temperature,and force.It is significant to investigate the failure mechanisms of various factors for the failure analysis of interconnections in power devices.This paper reviews the main failure modes of bonding wire and solder layer in the interconnection structure of power devices,and its failure mechanism.Then the reliability test method and failure analysis techniques of interconnection in power device are introduced.These methods are of great significance to the reliability analysis and life prediction of power devices.
文摘随着集成电路技术快速发展,芯片的集成度和密度越来越大,体积和功耗越来越小,IC领域提出了一种新型的超摩尔定律的芯片设计思路——系统级封装(System in Package,SiP)。要在有限的芯片管脚下完成对整个SiP电路系统的测试变得极具挑战,急需寻求一种新的测试方法。为此,文中提出了一种基于边界扫描测试方法,在严格遵循紧凑性和完备性的指标下,通过对现有自适应算法中快速生成测试矩阵算法的优化,完成SiP芯片的互连测试。对比分析优化前后各算法的混淆率和紧凑性指标,验证了使用低权值的等权值算法能有效地提高测试的性能。测试的仿真结果表明,基于边界扫描测试的低权值的等权值算法可以满足SiP的测试需求。
