Classical atomistic simulations based on the lattice dynalnics theory and the Born core-shell model are performed to systematically study the crystal structure and thermal properties of high-k Hfl-xSixO2. The coeffici...Classical atomistic simulations based on the lattice dynalnics theory and the Born core-shell model are performed to systematically study the crystal structure and thermal properties of high-k Hfl-xSixO2. The coefficients of thermal expansion, specific heat, Griineisen parameters, phonon densities of states and Debye temperatures are calculated at different temperatures and for different Si-doping concentrations. With the increase of the Si-doping concentration, the lattice constant decreases. At the same time, both the coefficient of thermal expansion and the specific heat at a constant volume of Hf1-mSixO2 also decreases. The Griineisen parameter is about 0.95 at temperatures less than 100 K. Compared with Si-doped HfO2, pure HfO2 has a higher Debye temperature when the temperature is less than 25 K, while it has lower Debye temperature when the temperature is higher than 50 K. Some simulation results fit well with the experimental data. We expect that our results will be helpful for understanding the local lattice structure and thermal properties of Hf1-mSixO2.展开更多
Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high perfor...Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high performance complementary metal-oxide-semiconductor(CMOS) circuits. Down scaling metal-oxide-semiconductor field-effect transistors(MOSFETs) into the deep submicron/nanometer regime forces the source(S) and drain(D) series resistance to become comparable with the channel resistance and thus it cannot be neglected. Owing to the persisting technological importance of strained Si devices, in this work, we propose a multi-iterative technique for evaluating the performance of strained-Si/strained-Si_(1-y)Ge_y/relaxed-Si_(1-x)Ge_x MOSFETs and its related circuits in the presence of S/D series resistance, leading to the development of a simulator that can faithfully plot the performance of the device and related digital circuits. The impact of strain on device/circuit performance is also investigated with emphasis on metal gate and high-k dielectric materials.展开更多
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 10964003 and 11164014)the Natural Science Foundation of Gansu Province, China (Grant No. 096RJZA102)+1 种基金the Specialized Research Fund for the Doctoral Program of Higher Education, China (Grant No. 20096201120002)the China Postdoctoral Science Foundation (Grant Nos. 20100470886 and 201104324)
文摘Classical atomistic simulations based on the lattice dynalnics theory and the Born core-shell model are performed to systematically study the crystal structure and thermal properties of high-k Hfl-xSixO2. The coefficients of thermal expansion, specific heat, Griineisen parameters, phonon densities of states and Debye temperatures are calculated at different temperatures and for different Si-doping concentrations. With the increase of the Si-doping concentration, the lattice constant decreases. At the same time, both the coefficient of thermal expansion and the specific heat at a constant volume of Hf1-mSixO2 also decreases. The Griineisen parameter is about 0.95 at temperatures less than 100 K. Compared with Si-doped HfO2, pure HfO2 has a higher Debye temperature when the temperature is less than 25 K, while it has lower Debye temperature when the temperature is higher than 50 K. Some simulation results fit well with the experimental data. We expect that our results will be helpful for understanding the local lattice structure and thermal properties of Hf1-mSixO2.
文摘Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high performance complementary metal-oxide-semiconductor(CMOS) circuits. Down scaling metal-oxide-semiconductor field-effect transistors(MOSFETs) into the deep submicron/nanometer regime forces the source(S) and drain(D) series resistance to become comparable with the channel resistance and thus it cannot be neglected. Owing to the persisting technological importance of strained Si devices, in this work, we propose a multi-iterative technique for evaluating the performance of strained-Si/strained-Si_(1-y)Ge_y/relaxed-Si_(1-x)Ge_x MOSFETs and its related circuits in the presence of S/D series resistance, leading to the development of a simulator that can faithfully plot the performance of the device and related digital circuits. The impact of strain on device/circuit performance is also investigated with emphasis on metal gate and high-k dielectric materials.
