电力线载波通信(PLC)信道不是专门为通信而设计的,因此在PLC信道中通常存在较大的噪声和干扰。通过配置模拟前端(analog front end,AFE)参数可以滤除不同频率的信道噪声和干扰,但这会增加电路设计难度和硬件成本。基于等效复数基带(equi...电力线载波通信(PLC)信道不是专门为通信而设计的,因此在PLC信道中通常存在较大的噪声和干扰。通过配置模拟前端(analog front end,AFE)参数可以滤除不同频率的信道噪声和干扰,但这会增加电路设计难度和硬件成本。基于等效复数基带(equivalent complex baseband,ECB)和奈奎斯特加窗技术,提出了一种新的数字前端(digital front end,DFE)结构,接收端加窗技术不仅能够有效地抑制频带外窄带干扰,消除相邻频段PLC系统或无线系统的影响,而且能够降低模拟前端的复杂性,节约设计成本。仿真结果表明:通过奈奎斯特窗,有利于把带内窄带干扰能量集中在较少的子载波上,便于窄带干扰的检测和消除,提高系统的性能。通过现场测试,进一步验证了所提出的数字前端技术的有效性。展开更多
The BETA application-specific integrated circuit(ASIC)is a fully programmable chip designed to amplify,shape and digitize the signal of up to 64 Silicon photomultiplier(SiPM)channels,with a power consumption of approx...The BETA application-specific integrated circuit(ASIC)is a fully programmable chip designed to amplify,shape and digitize the signal of up to 64 Silicon photomultiplier(SiPM)channels,with a power consumption of approximately~1 mW/channel.Owing to its dual-path gain,the BETA chip is capable of resolving single photoelectrons(phes)with a signal-to-noise ratio(SNR)>5 while simultaneously achieving a dynamic range of~4000 phes.Thus,BETA can provide a cost-effective solution for the readout of SiPMs in space missions and other applications with a maximum rate below 10 kHz.In this study,we describe the key characteristics of the BETA ASIC and present an evaluation of the performance of its 16-channel version,which is implemented using 130 nm technology.The ASIC also contains two discriminators that can provide trigger signals with a time jitter down to 400 ps FWHM for 10 phes.The linearity error of the charge gain measurement was less than 2%for a dynamic range as large as 15 bits.展开更多
系统基于MVC模式JavaEE技术,使用MyEclipse 2017 CI 10编译器,采用Mysql关系型数据库并结合HTML+CSS的前端技术进行系统开发,完成用户管理、新闻资讯管理、学生管理、教师管理、课程资料管理、留言管理、系统简介设置等功能模块。通过...系统基于MVC模式JavaEE技术,使用MyEclipse 2017 CI 10编译器,采用Mysql关系型数据库并结合HTML+CSS的前端技术进行系统开发,完成用户管理、新闻资讯管理、学生管理、教师管理、课程资料管理、留言管理、系统简介设置等功能模块。通过浏览器与服务器通信进行数据的交互,实现集人性化、高效率、便捷等优点于一身的在线教育平台。展开更多
文摘电力线载波通信(PLC)信道不是专门为通信而设计的,因此在PLC信道中通常存在较大的噪声和干扰。通过配置模拟前端(analog front end,AFE)参数可以滤除不同频率的信道噪声和干扰,但这会增加电路设计难度和硬件成本。基于等效复数基带(equivalent complex baseband,ECB)和奈奎斯特加窗技术,提出了一种新的数字前端(digital front end,DFE)结构,接收端加窗技术不仅能够有效地抑制频带外窄带干扰,消除相邻频段PLC系统或无线系统的影响,而且能够降低模拟前端的复杂性,节约设计成本。仿真结果表明:通过奈奎斯特窗,有利于把带内窄带干扰能量集中在较少的子载波上,便于窄带干扰的检测和消除,提高系统的性能。通过现场测试,进一步验证了所提出的数字前端技术的有效性。
基金support from Grant PID2020-116075GB-C21funded by MCIN/AEI/10.13039/501100011033+1 种基金by“ERDF A way of making Europe”under Grant PID2020-116075GB-C21They also acknowledge financial support from the State Agency for Research of the Spanish Ministry of Science and Innovation through the“Unit of Excellence Maria de Maeztu 2020-2023”award to the Institute of Cosmos Sciences(CEX2019-000918-M)。
文摘The BETA application-specific integrated circuit(ASIC)is a fully programmable chip designed to amplify,shape and digitize the signal of up to 64 Silicon photomultiplier(SiPM)channels,with a power consumption of approximately~1 mW/channel.Owing to its dual-path gain,the BETA chip is capable of resolving single photoelectrons(phes)with a signal-to-noise ratio(SNR)>5 while simultaneously achieving a dynamic range of~4000 phes.Thus,BETA can provide a cost-effective solution for the readout of SiPMs in space missions and other applications with a maximum rate below 10 kHz.In this study,we describe the key characteristics of the BETA ASIC and present an evaluation of the performance of its 16-channel version,which is implemented using 130 nm technology.The ASIC also contains two discriminators that can provide trigger signals with a time jitter down to 400 ps FWHM for 10 phes.The linearity error of the charge gain measurement was less than 2%for a dynamic range as large as 15 bits.
文摘系统基于MVC模式JavaEE技术,使用MyEclipse 2017 CI 10编译器,采用Mysql关系型数据库并结合HTML+CSS的前端技术进行系统开发,完成用户管理、新闻资讯管理、学生管理、教师管理、课程资料管理、留言管理、系统简介设置等功能模块。通过浏览器与服务器通信进行数据的交互,实现集人性化、高效率、便捷等优点于一身的在线教育平台。
