单粒子瞬态(SET)的电路仿真通常是注入双指数电流源来模拟,然而,纳米FinFET器件的SET采用单个双指数电流源模拟会带来较大误差。TCAD仿真结果较准确,但耗时较长,为了较为准确地电路仿真SET,提出了一种SET的复合双指数电流源模型。利用T...单粒子瞬态(SET)的电路仿真通常是注入双指数电流源来模拟,然而,纳米FinFET器件的SET采用单个双指数电流源模拟会带来较大误差。TCAD仿真结果较准确,但耗时较长,为了较为准确地电路仿真SET,提出了一种SET的复合双指数电流源模型。利用TCAD对电学特性校准的14 nm SOI FinFET器件的SET进行仿真,通过分析瞬态电流波形,对比双指数模型特点,提取特征参数,并利用遗传算法对模型参数进行优化处理,得到了关于线性能量转移(LET)的复合双电流源参数的解析模型。利用此复合双指数电流源模型与TCAD得到的瞬态电流波形、峰值和收集电荷量进行对比检验。结果显示,本文模型得到的SET电流波形与TCAD的基本吻合,与TCAD相比,模型的峰值电流的平均误差和最大误差分别为3.00%、5.06%;收集电荷量的平均误差和最大误差分别为4.02%、7.17%。展开更多
In this paper, we investigate the performance of the bulk fin field effect transistor （FinFET） through a three- dimensional （3D） full band Monte Carlo simulator with quantum correction. Several scattering mechanis...In this paper, we investigate the performance of the bulk fin field effect transistor （FinFET） through a three- dimensional （3D） full band Monte Carlo simulator with quantum correction. Several scattering mechanisms, such as the acoustic and optical phonon scattering, the ionized impurity scattering, the impact ionization scattering and the surface roughness scattering are considered in our simulator. The effects of the substrate bias and the surface roughness scattering near the Si/SiO2 interface on the performance of bulk FinFET are mainly discussed in our work. Our results show that the on-current of bulk FinFET is sensitive to the surface roughness and that we can reduce the substrate leakage current by modulating the substrate bias voltage.展开更多
A novel three-dimensional device structure for a carbon nanotube （CNT） fin field-effect transistor （FinFET） is proposed and evaluated. We evaluated the potential of the CNT FinFET compared with a Si FinFET at a 22...A novel three-dimensional device structure for a carbon nanotube （CNT） fin field-effect transistor （FinFET） is proposed and evaluated. We evaluated the potential of the CNT FinFET compared with a Si FinFET at a 22-nm node at the circuit level using three performance metrics including propagation delay, total power dissipation, and energy-delay product （EDP）. Compared with a Si FinFET, the CNT FinFET presents obvious advantages in speed and EDP arising from its almost much larger current density but also results in a higher total power dissipation, especially at a low threshold voltage （V~ = 1/3Vaa）. A suitable improvement in Vth can effectively contribute to a significant suppression of leakage current and power dissipation, and then an obvious optimization is obtained in the EDP with an acceptable sacrifice in speed. In particular, CNT FinFETs with optimized threshold voltages can provide an EDP advantage of approximately 50 times over Si FinFETs under a low supply voltage （Vdd -- 0.4 V）, suggesting great potential for CNT FinFET-based integrated circuits.展开更多
文摘单粒子瞬态(SET)的电路仿真通常是注入双指数电流源来模拟,然而,纳米FinFET器件的SET采用单个双指数电流源模拟会带来较大误差。TCAD仿真结果较准确,但耗时较长,为了较为准确地电路仿真SET,提出了一种SET的复合双指数电流源模型。利用TCAD对电学特性校准的14 nm SOI FinFET器件的SET进行仿真,通过分析瞬态电流波形,对比双指数模型特点,提取特征参数,并利用遗传算法对模型参数进行优化处理,得到了关于线性能量转移(LET)的复合双电流源参数的解析模型。利用此复合双指数电流源模型与TCAD得到的瞬态电流波形、峰值和收集电荷量进行对比检验。结果显示,本文模型得到的SET电流波形与TCAD的基本吻合,与TCAD相比,模型的峰值电流的平均误差和最大误差分别为3.00%、5.06%;收集电荷量的平均误差和最大误差分别为4.02%、7.17%。
基金Project supported by the National Basic Research Program of China (Grant No. 2011CBA00604)
文摘In this paper, we investigate the performance of the bulk fin field effect transistor （FinFET） through a three- dimensional （3D） full band Monte Carlo simulator with quantum correction. Several scattering mechanisms, such as the acoustic and optical phonon scattering, the ionized impurity scattering, the impact ionization scattering and the surface roughness scattering are considered in our simulator. The effects of the substrate bias and the surface roughness scattering near the Si/SiO2 interface on the performance of bulk FinFET are mainly discussed in our work. Our results show that the on-current of bulk FinFET is sensitive to the surface roughness and that we can reduce the substrate leakage current by modulating the substrate bias voltage.
文摘A novel three-dimensional device structure for a carbon nanotube （CNT） fin field-effect transistor （FinFET） is proposed and evaluated. We evaluated the potential of the CNT FinFET compared with a Si FinFET at a 22-nm node at the circuit level using three performance metrics including propagation delay, total power dissipation, and energy-delay product （EDP）. Compared with a Si FinFET, the CNT FinFET presents obvious advantages in speed and EDP arising from its almost much larger current density but also results in a higher total power dissipation, especially at a low threshold voltage （V~ = 1/3Vaa）. A suitable improvement in Vth can effectively contribute to a significant suppression of leakage current and power dissipation, and then an obvious optimization is obtained in the EDP with an acceptable sacrifice in speed. In particular, CNT FinFETs with optimized threshold voltages can provide an EDP advantage of approximately 50 times over Si FinFETs under a low supply voltage （Vdd -- 0.4 V）, suggesting great potential for CNT FinFET-based integrated circuits.
