A novel full-digital integrator has been developed for the magnetic diagnostics in HL-2A. Based on the pipeline processing of the field-programmable gate array and high-speed PCI extensions for instrumentation platfor...A novel full-digital integrator has been developed for the magnetic diagnostics in HL-2A. Based on the pipeline processing of the field-programmable gate array and high-speed PCI extensions for instrumentation platform, the digital integrator has realized octal-channel10-k Hz real-time integration and data transmission. In order to reduce the integration drift, a 24-bit analog-todigital converter and simple analog processing circuits are applied for high-precision sampling, while certain correction algorithms are used to minimize the drift. With simple and highly integrated circuits and high-performance digital processor, the digital integrator is of high stability and functional expansibility which greatly simplifies the operation procedure. The digital integrator has been tested in the plasma discharge experiments, and the experimental results have confirmed that the drift performance and accuracy of the digital integrator could fully meet the requirements of HL-2A.展开更多
以非线性组合函数和线性反馈移位寄存器(LFSR:L inear Feedback Sh iftRegisters)为基础,利用可编程逻辑门阵列(FPGA:F ield-Programm ab le Gate Array)设计了一个高速加密芯片。该芯片既能满足密码学领域对密钥序列的高质量要求,又能...以非线性组合函数和线性反馈移位寄存器(LFSR:L inear Feedback Sh iftRegisters)为基础,利用可编程逻辑门阵列(FPGA:F ield-Programm ab le Gate Array)设计了一个高速加密芯片。该芯片既能满足密码学领域对密钥序列的高质量要求,又能满足保密通信领域高速度要求。介绍了加密芯片的设计理论、设计过程、加密芯片安全性分析和硬件实现,最后对密钥流进行了随机性统计测试。展开更多
We present a fractional-order three-dimensional chaotic system, which can generate four-wing chaotic attractor. Dy- namics of the fractional-order system is investigated by numerical simulations. To rigorously verify ...We present a fractional-order three-dimensional chaotic system, which can generate four-wing chaotic attractor. Dy- namics of the fractional-order system is investigated by numerical simulations. To rigorously verify the chaos properties of this system, the existence of horseshoe in the four-wing attractor is presented. Firstly, a Poincar6 section is selected properly, and a first-return Poincar6 map is established. Then, a one-dimensional tensile horseshoe is discovered, which verifies the chaos existence of the system in mathematical view. Finally, the fractional-order chaotic attractor is imple- mented physically with a field-programmable gate array （FPGA） chip, which is useful in further engineering applications of information encryption and secure communications.展开更多
Abstract To improve the reliability of spaceborne electronic systems, a fault-tolerant strategy of selective triple modular redundancy （STMR） based on multi-objective optimization and evolvable hardware （EHW） agai...Abstract To improve the reliability of spaceborne electronic systems, a fault-tolerant strategy of selective triple modular redundancy （STMR） based on multi-objective optimization and evolvable hardware （EHW） against single-event upsets （SEUs） for circuits implemented on field pro- grammable gate arrays （FPGAs） based on static random access memory （SRAM） is presented in this paper. Various topologies of circuit with the same functionality are evolved using EHW firstly. Then the SEU-sensitive gates of each circuit are identified using signal probabilities of all the lines in it, and each circuit is hardened against SEUs by selectively applying triple modular redundancy （TMR） to these SEU-sensitive gates. Afterward, each circuit hardened has been evaluated by SEU Simulation, and the multi-objective optimization technology is introduced to optimize the area overhead and the number of functional errors of all the circuits, The proposed fault-tolerant strategy is tested on four circuits from microelectronics center of North Carolina （MCNC） benchmark suite. The experimental results show that it can generate innovative trade-off solutions to compromise between hardware resource consumption and system reliability. The maximum savings in the area overhead of the STMR circuit over the full TMR design is 58% with the same SEU immunity.展开更多
基金supported by National Natural Science Foundation of China(No.11375195)National Magnetic Confinement Fusion Energy Development Research(No.2013GB104003)
文摘A novel full-digital integrator has been developed for the magnetic diagnostics in HL-2A. Based on the pipeline processing of the field-programmable gate array and high-speed PCI extensions for instrumentation platform, the digital integrator has realized octal-channel10-k Hz real-time integration and data transmission. In order to reduce the integration drift, a 24-bit analog-todigital converter and simple analog processing circuits are applied for high-precision sampling, while certain correction algorithms are used to minimize the drift. With simple and highly integrated circuits and high-performance digital processor, the digital integrator is of high stability and functional expansibility which greatly simplifies the operation procedure. The digital integrator has been tested in the plasma discharge experiments, and the experimental results have confirmed that the drift performance and accuracy of the digital integrator could fully meet the requirements of HL-2A.
文摘以非线性组合函数和线性反馈移位寄存器(LFSR:L inear Feedback Sh iftRegisters)为基础,利用可编程逻辑门阵列(FPGA:F ield-Programm ab le Gate Array)设计了一个高速加密芯片。该芯片既能满足密码学领域对密钥序列的高质量要求,又能满足保密通信领域高速度要求。介绍了加密芯片的设计理论、设计过程、加密芯片安全性分析和硬件实现,最后对密钥流进行了随机性统计测试。
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61502340 and 61374169)the Application Base and Frontier Technology Research Project of Tianjin,China(Grant No.15JCYBJC51800)the South African National Research Foundation Incentive Grants(Grant No.81705)
文摘We present a fractional-order three-dimensional chaotic system, which can generate four-wing chaotic attractor. Dy- namics of the fractional-order system is investigated by numerical simulations. To rigorously verify the chaos properties of this system, the existence of horseshoe in the four-wing attractor is presented. Firstly, a Poincar6 section is selected properly, and a first-return Poincar6 map is established. Then, a one-dimensional tensile horseshoe is discovered, which verifies the chaos existence of the system in mathematical view. Finally, the fractional-order chaotic attractor is imple- mented physically with a field-programmable gate array （FPGA） chip, which is useful in further engineering applications of information encryption and secure communications.
基金supported by National Natural Science Foundation of China(No.61402226)supported by the Fundamental Research Funds for the Central Universities of China(No.NS2014036)
文摘Abstract To improve the reliability of spaceborne electronic systems, a fault-tolerant strategy of selective triple modular redundancy （STMR） based on multi-objective optimization and evolvable hardware （EHW） against single-event upsets （SEUs） for circuits implemented on field pro- grammable gate arrays （FPGAs） based on static random access memory （SRAM） is presented in this paper. Various topologies of circuit with the same functionality are evolved using EHW firstly. Then the SEU-sensitive gates of each circuit are identified using signal probabilities of all the lines in it, and each circuit is hardened against SEUs by selectively applying triple modular redundancy （TMR） to these SEU-sensitive gates. Afterward, each circuit hardened has been evaluated by SEU Simulation, and the multi-objective optimization technology is introduced to optimize the area overhead and the number of functional errors of all the circuits, The proposed fault-tolerant strategy is tested on four circuits from microelectronics center of North Carolina （MCNC） benchmark suite. The experimental results show that it can generate innovative trade-off solutions to compromise between hardware resource consumption and system reliability. The maximum savings in the area overhead of the STMR circuit over the full TMR design is 58% with the same SEU immunity.
