The paper presents a new architecture composed of bit plane-parallel coder for Embedded Block Coding with Optimized Truncation (EBCOT) entropy encoder used in JPEG2000. In the architecture, the coding information of e...The paper presents a new architecture composed of bit plane-parallel coder for Embedded Block Coding with Optimized Truncation (EBCOT) entropy encoder used in JPEG2000. In the architecture, the coding information of each bit plane can be obtained simultaneously and processed parallel. Compared with other architectures, it has advantages of high parallelism, and no waste clock cycles for a single point. The experimental results show that it reduces the processing time about 86% than that of bit plane sequential scheme. A Field Programmable Gate Array (FPGA) prototype chip is designed and simulation results show that it can process 512×512 gray-scaled images with more than 30 frames per second at 52MHz.展开更多
In this study, we present a miniOS kernel implemented via analysis of the context switching, the scheduler, and the memory management of the original OS kernel for an embedded system based on ARM core. Since this is a...In this study, we present a miniOS kernel implemented via analysis of the context switching, the scheduler, and the memory management of the original OS kernel for an embedded system based on ARM core. Since this is a large subject, we have limited our scope to them only that made up an embedded operating system. The implemented miniOS kernel is composed only by them, to the exclusion of all other functions of the original kernel. Our goal is to modify the OS kernel depending on the product function. The implementation method of the miniOS kernel can be applicable to any OS being mounted based on the ARM core. Modifying the kernel depending on the product function can improve the OS booting speed as well as save the system memory. The functions of the scheduler, the context switching, and the memory management are described with the source in each section. The miniOS kernel was implemented in the Assembly and C language and was verified through the build and the test. The results are shown in the Section 5.展开更多
基金Supported in part by the "863" Program (No.2003 AA1ZB10)
文摘The paper presents a new architecture composed of bit plane-parallel coder for Embedded Block Coding with Optimized Truncation (EBCOT) entropy encoder used in JPEG2000. In the architecture, the coding information of each bit plane can be obtained simultaneously and processed parallel. Compared with other architectures, it has advantages of high parallelism, and no waste clock cycles for a single point. The experimental results show that it reduces the processing time about 86% than that of bit plane sequential scheme. A Field Programmable Gate Array (FPGA) prototype chip is designed and simulation results show that it can process 512×512 gray-scaled images with more than 30 frames per second at 52MHz.
文摘In this study, we present a miniOS kernel implemented via analysis of the context switching, the scheduler, and the memory management of the original OS kernel for an embedded system based on ARM core. Since this is a large subject, we have limited our scope to them only that made up an embedded operating system. The implemented miniOS kernel is composed only by them, to the exclusion of all other functions of the original kernel. Our goal is to modify the OS kernel depending on the product function. The implementation method of the miniOS kernel can be applicable to any OS being mounted based on the ARM core. Modifying the kernel depending on the product function can improve the OS booting speed as well as save the system memory. The functions of the scheduler, the context switching, and the memory management are described with the source in each section. The miniOS kernel was implemented in the Assembly and C language and was verified through the build and the test. The results are shown in the Section 5.
