The effect of drain-source voltage on A1GaAs/InGaAs PHEMTs thermal resistance is studied by experimental measuring and simulation. The result shows that A1GaAs/InGaAs PHEMTs thermal resistance presents a downward tren...The effect of drain-source voltage on A1GaAs/InGaAs PHEMTs thermal resistance is studied by experimental measuring and simulation. The result shows that A1GaAs/InGaAs PHEMTs thermal resistance presents a downward trend under the same power dissipation when the drain-source voltage （VDs） is decreased. Moreover, the relatively low VDS and large drain-source current （IDs） result in a lower thermal resistance. The chip-level and package-level thermal resistance have been extracted by the structure function method. The simulation result indicated that the high electric field occurs at the gate contact where the temperature rise occurs. A relatively low VDS leads to a relatively low electric field, which leads to the decline of the thermal resistance.展开更多
SiC MOSFET因其高击穿电压、高开关速度、低导通损耗等性能优势而被广泛应用于各类电力电子变换器中。然而,由于其短路耐受时间仅为2~7μs,且随母线电压升高而缩短,快速可靠的短路保护电路已成为其推广应用的关键技术之一。为应对不同...SiC MOSFET因其高击穿电压、高开关速度、低导通损耗等性能优势而被广泛应用于各类电力电子变换器中。然而,由于其短路耐受时间仅为2~7μs,且随母线电压升高而缩短,快速可靠的短路保护电路已成为其推广应用的关键技术之一。为应对不同母线电压下的Si C MOSFET短路故障,文中提出一种基于漏源电压积分的自适应快速短路保护方法(drain-sourcevoltageintegration-basedadaptivefast short-circuit protection method,DSVI-AFSCPM),研究所提出的DSVI-AFSCPM在硬开关短路(hardswitchingfault,HSF)和负载短路(fault under load,FUL)条件下的保护性能,进而研究不同母线电压对DSVI-AFSCPM的作用机理。同时,探究Si CMOSFET工作温度对其响应速度的影响。最后,搭建实验平台,对所提出的DSVI-AFSCPM在发生硬开关短路和负载短路时不同母线电压、不同工作温度下的保护性能进行实验测试。实验结果表明,所提出的DSVI-AFSCPM在不同母线电压下具有良好的保护速度自适应性,即母线电压越高,短路保护速度越快,并且其响应速度受Si CMOSFET工作温度影响较小,两种短路工况下工作温度从25℃变化到125℃,短路保护时间变化不超过90 ns。因此,该文为Si CMOSFET在不同母线电压下的可靠使用提供一定技术支撑。展开更多
基金Project supported by the National Natural Science Foundation of China(Nos.61376077,61201046,61204081)the Beijing Natural Science Foundation(Nos.4132022,4122005)+1 种基金the Guangdong Strategic Emerging Industry Project of China(No.2012A080304003)the Doctoral Fund of Innovation of Beijing University of Technology
文摘The effect of drain-source voltage on A1GaAs/InGaAs PHEMTs thermal resistance is studied by experimental measuring and simulation. The result shows that A1GaAs/InGaAs PHEMTs thermal resistance presents a downward trend under the same power dissipation when the drain-source voltage （VDs） is decreased. Moreover, the relatively low VDS and large drain-source current （IDs） result in a lower thermal resistance. The chip-level and package-level thermal resistance have been extracted by the structure function method. The simulation result indicated that the high electric field occurs at the gate contact where the temperature rise occurs. A relatively low VDS leads to a relatively low electric field, which leads to the decline of the thermal resistance.
