Readout electronics is developed for a prototype time-of-flight(TOF) ion composition spectrometer for in situ measurement of the mass/charge distributions of major ion species from 200 to 100 ke V/e in space plasma.By...Readout electronics is developed for a prototype time-of-flight(TOF) ion composition spectrometer for in situ measurement of the mass/charge distributions of major ion species from 200 to 100 ke V/e in space plasma.By utilizing a constant fraction discriminator(CFD) and time-to-digital converter(TDC), challenging dynamic range measurements were performed with high time resolution and event rates. CFD was employed to discriminate the TOF signals from the micro-channel plate and channel electron multipliers. TDC based on the combination of counter and OR-gate delay chain was designed in a highreliability flash field programmable gate array. Owing to the non-uniformity of the delay chain, a correction algorithm based on integral nonlinearity compensation was implemented to reduce the time uncertainty. The test results showed that the electronics achieved a low timingerror of < 200 ps in the input range from 35 to 500 m V for the CFD, and a time resolution of ～550 ps with time uncertainty < 180 ps after correction and a time range of6.4 ls for the TDC. The TOF spectrum from an electron beam experiment of the impacting N_2 gas further indicated the good performance of this readout electronic.展开更多
设计了一种基于数字COT控制的DC-DC变换器。通过分时复用的方法,采用单个ADC实现输入/输出电压和误差电压的量化,并通过内部数字信号计算得到电感电流信息。为克服ADC量程和精度之间的矛盾,使用PGA和DAC实现对6 bit ADC量程的扩展。Buc...设计了一种基于数字COT控制的DC-DC变换器。通过分时复用的方法,采用单个ADC实现输入/输出电压和误差电压的量化,并通过内部数字信号计算得到电感电流信息。为克服ADC量程和精度之间的矛盾,使用PGA和DAC实现对6 bit ADC量程的扩展。Buck变换器在输入电压3.3 V、输出电压1.8 V、开关频率1 MHz下进行了仿真验证,输入电压阶跃响应时间从276μs/324μs下降到几乎无影响,负载阶跃响应时间达到39μs/39μs,电源调整率为0.14%,负载调整率为0.14%,输出精度达到了4 mV。展开更多
Sample-time error between channels degrades the resolution of time-interleaved analog-to-digital converters （TIADCs）.A calibration method implemented in mixed circuits with low complexity and fast convergence is pro...Sample-time error between channels degrades the resolution of time-interleaved analog-to-digital converters （TIADCs）.A calibration method implemented in mixed circuits with low complexity and fast convergence is proposed in this paper.The algorithm for detecting sample-time error is based on correlation and widely applied to wide-sense stationary input signals.The detected sample-time error is corrected by a voltage-controlled sampling switch.The experimental result of a 2-channel 200-MS/s 14-bit TIADC shows that the signal-to-noise and distortion ratio improves by 19.1 dB,and the spurious-free dynamic range improves by 34.6 dB for a 70.12-MHz input after calibration.The calibration convergence time is about 20000 sampling intervals.展开更多
Time to digital converter(TDC)is a key block for time-gated single photon avalanche diode(SPAD)arrays for Raman spectroscopy that applicable in the agricultural products and food analysis.In this paper a new dual slop...Time to digital converter(TDC)is a key block for time-gated single photon avalanche diode(SPAD)arrays for Raman spectroscopy that applicable in the agricultural products and food analysis.In this paper a new dual slope time to digital converter that employs the time to voltage conversion and integrating techniques for digitizing the time interval input signals is presented.The reference clock frequency of the TDC is 100 MHz and the input range is theoretically unlimited.The proposed converter features high accuracy,very small average error and high linear range.Also this converter has some advantages such as low circuit complexity,low power consumption and low sensitive to the temperature,power supply and process changes(PVT)compared with the time to digital converters that used preceding conversion techniques.The proposed converter uses an indirect time to digital conversion method.Therefore,our converter has the appropriate linearity without extra elements.In order to evaluate the proposed idea,an integrating time to digital converter is designed in 0.18 lm CMOS technology and was simulated by Hspice.Comparison of the theoretical and simulation results confirms the proposed TDC operation;therefore,the proposed converter is very convenient for applications which have average speed and low variations in the signal amplitude such as biomedical signals.展开更多
A high resolution and fast conversion rate time-to-digital converter （TDC） design based on time amplifier （TA） is proposed. The pulse-train TA employs a two-step scheme. The input time interval is first amplified ...A high resolution and fast conversion rate time-to-digital converter （TDC） design based on time amplifier （TA） is proposed. The pulse-train TA employs a two-step scheme. The input time interval is first amplified by a N-times TA and the effective time is extracted in pulse-train using a time-register. Then the resulted interval is further amplified by the other pulse-train amplifier to obtain the final result. The two-step TA can thus achieve large gain that is critical for high resolution TDC. Simulation results in 1.2 V, 65 nm technology showed that for a 10 bit TDC, a resolution of 0. 8 ps and a conversion rate of 150 MS/s are achieved while consuming 2. 1 mW power consumption.展开更多
This paper presents a differential successive approximation register analog-to-digital converter（SAR ADC） with a novel time-domain comparator design for wireless sensor networks.The prototype chip has been implement...This paper presents a differential successive approximation register analog-to-digital converter（SAR ADC） with a novel time-domain comparator design for wireless sensor networks.The prototype chip has been implemented in the UMC 0.18-μm 1P6M CMOS process.The proposed ADC achieves a peak ENOB of 7.98 at an input frequency of 39.7 kHz and sampling rate of 180 kHz.With the Nyquist input frequency,68.49-dB SFDR,7.97-ENOB is achieved.A simple quadrate layout is adopted to ease the routing complexity of the common-centroid symmetry layout.The ADC maintains a maximum differential nonlinearity of less than 0.08 LSB and integral nonlinearity less than 0.34 LSB by this type of layout.展开更多
A 1-V third order one-bit continuous-time（CT） EA modulator is presented. Designed in the SMIC mixedsignal 0.13-μm CMOS process, the modulator utilizes active RC integrators to implement the loop filter. An efficien...A 1-V third order one-bit continuous-time（CT） EA modulator is presented. Designed in the SMIC mixedsignal 0.13-μm CMOS process, the modulator utilizes active RC integrators to implement the loop filter. An efficient circuit design methodology for the CT ZA modulator is proposed and verified. Low power dissipation is achieved through the use of two-stage class A/AB amplifiers. The presented modulator achieves 81.4-dB SNDR and 85-dB dynamic range in a 20-kHz bandwidth with an over sampling ratio of 128. The total power consumption of the modulator is only 60 μW from a 1-V power supply and the prototype occupies an active area of 0.12 mm^2.展开更多
A gated ring oscillator(GRO) based time-to-digital converter(TDC) is presented.To enhance the resolution of the TDC,a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input sta...A gated ring oscillator(GRO) based time-to-digital converter(TDC) is presented.To enhance the resolution of the TDC,a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input stage is also presented to equivalently amplify the input time difference with a gain of 2.The GRO based TDC circuit is fabricated in TSMC 65 nm CMOS technology and the core area is about 0.02 mm^2.According to the measurement results,the effective resolution of this circuit is better than 4.22 ps under a 50 MHz clock frequency. With a 1 ns input range,the maximum clock frequency of this circuit is larger than 200 MHz.Under a 1 V power supply,with a 200-800 ps input time difference,the measured power consumption is 1.24 to 1.72 mW at 50 MHz clock frequency and 1.73 to 2.20 mW at 200 MHz clock frequency.展开更多
A fast-locking all-digital delay-locked loop（ADDLL） is proposed for the DDR SDRAM controller interface in a field programmable gate array（FPGA）.The ADDLL performs a 90°phase-shift so that the data strobe（DQS...A fast-locking all-digital delay-locked loop（ADDLL） is proposed for the DDR SDRAM controller interface in a field programmable gate array（FPGA）.The ADDLL performs a 90°phase-shift so that the data strobe（DQS） can enlarge the data valid window in order to minimize skew.In order to further reduce the locking time and to prevent the harmonic locking problem,a time-to-digital converter（TDC） is proposed.A duty cycle corrector（DCC） is also designed in the ADDLL to adjust the output duty cycle to 50%.The ADDLL,implemented in a commercial 0.13μm CMOS process,occupies a total of 0.017 mm^2 of active area.Measurement results show that the ADDLL has an operating frequency range of 75 to 350 MHz and a total delay resolution of 15 ps.The time interval error（TIE） of the proposed circuit is 60.7 ps.展开更多
A sampling switch with an embedded digital-to-skew converter(DSC) is presented.The proposed switch eliminates time-interleaved ADCs' skews by adjusting the boosted voltage.A similar bridged capacitors' charge ...A sampling switch with an embedded digital-to-skew converter(DSC) is presented.The proposed switch eliminates time-interleaved ADCs' skews by adjusting the boosted voltage.A similar bridged capacitors' charge sharing structure is used to minimize the area.The circuit is fabricated in a 0.18μm CMOS process and achieves sub-1 ps resolution and 200 ps timing range at a rate of 100 MS/s.The power consumption is 430μW at maximum.The measurement result also includes a 2-channel 14-bit 100 MS/s time-interleaved ADCs(TI-ADCs) with the proposed DSC switch's demonstration.This scheme is widely applicable for the clock skew and aperture error calibration demanded in TI-ADCs and SHA-less ADCs.展开更多
In a time-interleaved analog-to-digital converter （TI ADC）, several individual ADCs operate in parallel to achieve a higher sampling rate. Low power consumption as well as good linearity can be obtained by applying ...In a time-interleaved analog-to-digital converter （TI ADC）, several individual ADCs operate in parallel to achieve a higher sampling rate. Low power consumption as well as good linearity can be obtained by applying successive approximation register （SAR） converters as sub-channel ADCs. In spite of the advantages, this structure suffers from three mismatches, which are offset mismatch, gain mismatch, and time skew. This paper focuses on a TI SAR ADC with a number of channels. The mismatch effects in the frequency domain are analyzed and the derived close form formulas are verified based on Matlab. In addition, we clarify that the standard deviation of DNL and INL of an M-channel TI ADC is reduced by a factor of ~ compared to a single channel ADC. The formulas can be used to derive the corresponding requirements when designing a TI ADC. Our analysis process is able to inform the study of calibration algorithms.展开更多
Recently, real-time simulation of renewable energy sources are indispensible for evaluating the performance of the maximum power point tracking （MPPT） controller, especially in the photovoltaic （PV） system in orde...Recently, real-time simulation of renewable energy sources are indispensible for evaluating the performance of the maximum power point tracking （MPPT） controller, especially in the photovoltaic （PV） system in order to reduce cost in the testing phase. Nowadays, real time PV simulators are obtained by using analog and/or digital components. In this paper, a real-time simulation of a PV system with a boost converter was proposed using only the digital signal processor （DSP） processor with two DC voltage sources to emulate the temperature and irradiation in the PV system. A MATLAB/ Simulink environment was used to develop the real-time PV system with a boost converter into a C-program and build it into a DSP controller TMS320F28335. Besides, the performance of the real-time DSP-based PV was tested in different temperature and irradiation conditions to observe the P-V and V-I characteristics. Further, the performance of the PV with a boost converter was tested at different temperatures and irradiations using MPPT algorithms. This scheme was tested through simulation and the results were validated with that of standard conditions given in the PV data sheets. Implementation of this project helped to attract more researchers to study renewable energy applications without real sources. This might facilitate the study of PV systems in a real-time scenario and the evaluation of what should be expected for PV modules available in the market.展开更多
基金supported by the National Key Scientific Instrument and Equipment Development Projects of the National Natural Science Foundation of China(No.41327802)China Mars Project
文摘Readout electronics is developed for a prototype time-of-flight(TOF) ion composition spectrometer for in situ measurement of the mass/charge distributions of major ion species from 200 to 100 ke V/e in space plasma.By utilizing a constant fraction discriminator(CFD) and time-to-digital converter(TDC), challenging dynamic range measurements were performed with high time resolution and event rates. CFD was employed to discriminate the TOF signals from the micro-channel plate and channel electron multipliers. TDC based on the combination of counter and OR-gate delay chain was designed in a highreliability flash field programmable gate array. Owing to the non-uniformity of the delay chain, a correction algorithm based on integral nonlinearity compensation was implemented to reduce the time uncertainty. The test results showed that the electronics achieved a low timingerror of < 200 ps in the input range from 35 to 500 m V for the CFD, and a time resolution of ～550 ps with time uncertainty < 180 ps after correction and a time range of6.4 ls for the TDC. The TOF spectrum from an electron beam experiment of the impacting N_2 gas further indicated the good performance of this readout electronic.
基金supported by the National Natural Science Foundation of China(No.61006025)the Special Research Funds for Doctoral Program of Higher Education of China(No.20100071110026)
文摘Sample-time error between channels degrades the resolution of time-interleaved analog-to-digital converters （TIADCs）.A calibration method implemented in mixed circuits with low complexity and fast convergence is proposed in this paper.The algorithm for detecting sample-time error is based on correlation and widely applied to wide-sense stationary input signals.The detected sample-time error is corrected by a voltage-controlled sampling switch.The experimental result of a 2-channel 200-MS/s 14-bit TIADC shows that the signal-to-noise and distortion ratio improves by 19.1 dB,and the spurious-free dynamic range improves by 34.6 dB for a 70.12-MHz input after calibration.The calibration convergence time is about 20000 sampling intervals.
文摘Time to digital converter(TDC)is a key block for time-gated single photon avalanche diode(SPAD)arrays for Raman spectroscopy that applicable in the agricultural products and food analysis.In this paper a new dual slope time to digital converter that employs the time to voltage conversion and integrating techniques for digitizing the time interval input signals is presented.The reference clock frequency of the TDC is 100 MHz and the input range is theoretically unlimited.The proposed converter features high accuracy,very small average error and high linear range.Also this converter has some advantages such as low circuit complexity,low power consumption and low sensitive to the temperature,power supply and process changes(PVT)compared with the time to digital converters that used preceding conversion techniques.The proposed converter uses an indirect time to digital conversion method.Therefore,our converter has the appropriate linearity without extra elements.In order to evaluate the proposed idea,an integrating time to digital converter is designed in 0.18 lm CMOS technology and was simulated by Hspice.Comparison of the theoretical and simulation results confirms the proposed TDC operation;therefore,the proposed converter is very convenient for applications which have average speed and low variations in the signal amplitude such as biomedical signals.
基金supported by the National Natural Science Foundation of China ( 61774005)
文摘A high resolution and fast conversion rate time-to-digital converter （TDC） design based on time amplifier （TA） is proposed. The pulse-train TA employs a two-step scheme. The input time interval is first amplified by a N-times TA and the effective time is extracted in pulse-train using a time-register. Then the resulted interval is further amplified by the other pulse-train amplifier to obtain the final result. The two-step TA can thus achieve large gain that is critical for high resolution TDC. Simulation results in 1.2 V, 65 nm technology showed that for a 10 bit TDC, a resolution of 0. 8 ps and a conversion rate of 150 MS/s are achieved while consuming 2. 1 mW power consumption.
基金supported by the National Natural Science Foundation of China(No.60976032)
文摘This paper presents a differential successive approximation register analog-to-digital converter（SAR ADC） with a novel time-domain comparator design for wireless sensor networks.The prototype chip has been implemented in the UMC 0.18-μm 1P6M CMOS process.The proposed ADC achieves a peak ENOB of 7.98 at an input frequency of 39.7 kHz and sampling rate of 180 kHz.With the Nyquist input frequency,68.49-dB SFDR,7.97-ENOB is achieved.A simple quadrate layout is adopted to ease the routing complexity of the common-centroid symmetry layout.The ADC maintains a maximum differential nonlinearity of less than 0.08 LSB and integral nonlinearity less than 0.34 LSB by this type of layout.
基金supported by the National High Technology Research and Development Program of China(No.2008AA010702)
文摘A 1-V third order one-bit continuous-time（CT） EA modulator is presented. Designed in the SMIC mixedsignal 0.13-μm CMOS process, the modulator utilizes active RC integrators to implement the loop filter. An efficient circuit design methodology for the CT ZA modulator is proposed and verified. Low power dissipation is achieved through the use of two-stage class A/AB amplifiers. The presented modulator achieves 81.4-dB SNDR and 85-dB dynamic range in a 20-kHz bandwidth with an over sampling ratio of 128. The total power consumption of the modulator is only 60 μW from a 1-V power supply and the prototype occupies an active area of 0.12 mm^2.
基金supported by the Important National Science and Technology Specific Projects of China(No.2009ZX01031-003-002)
文摘A gated ring oscillator(GRO) based time-to-digital converter(TDC) is presented.To enhance the resolution of the TDC,a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input stage is also presented to equivalently amplify the input time difference with a gain of 2.The GRO based TDC circuit is fabricated in TSMC 65 nm CMOS technology and the core area is about 0.02 mm^2.According to the measurement results,the effective resolution of this circuit is better than 4.22 ps under a 50 MHz clock frequency. With a 1 ns input range,the maximum clock frequency of this circuit is larger than 200 MHz.Under a 1 V power supply,with a 200-800 ps input time difference,the measured power consumption is 1.24 to 1.72 mW at 50 MHz clock frequency and 1.73 to 2.20 mW at 200 MHz clock frequency.
基金Project supported by the Major National Scientific Research Plan of China(No.2011 CB933202)the National High Technology Research and Development Program of China(No.2008AA010701)
文摘A fast-locking all-digital delay-locked loop（ADDLL） is proposed for the DDR SDRAM controller interface in a field programmable gate array（FPGA）.The ADDLL performs a 90°phase-shift so that the data strobe（DQS） can enlarge the data valid window in order to minimize skew.In order to further reduce the locking time and to prevent the harmonic locking problem,a time-to-digital converter（TDC） is proposed.A duty cycle corrector（DCC） is also designed in the ADDLL to adjust the output duty cycle to 50%.The ADDLL,implemented in a commercial 0.13μm CMOS process,occupies a total of 0.017 mm^2 of active area.Measurement results show that the ADDLL has an operating frequency range of 75 to 350 MHz and a total delay resolution of 15 ps.The time interval error（TIE） of the proposed circuit is 60.7 ps.
基金supported by the National Natural Science Foundation of China(No.61006025)the Special Research Funds for Doctoral Program of Higher Education of China(No.20100071110026)
文摘A sampling switch with an embedded digital-to-skew converter(DSC) is presented.The proposed switch eliminates time-interleaved ADCs' skews by adjusting the boosted voltage.A similar bridged capacitors' charge sharing structure is used to minimize the area.The circuit is fabricated in a 0.18μm CMOS process and achieves sub-1 ps resolution and 200 ps timing range at a rate of 100 MS/s.The power consumption is 430μW at maximum.The measurement result also includes a 2-channel 14-bit 100 MS/s time-interleaved ADCs(TI-ADCs) with the proposed DSC switch's demonstration.This scheme is widely applicable for the clock skew and aperture error calibration demanded in TI-ADCs and SHA-less ADCs.
基金Project supported by the National Natural Science Foundation of China(Nos.61234002,61322405,61306044,61376033)the National High-Tech Program of China(No.2013AA014103)
文摘In a time-interleaved analog-to-digital converter （TI ADC）, several individual ADCs operate in parallel to achieve a higher sampling rate. Low power consumption as well as good linearity can be obtained by applying successive approximation register （SAR） converters as sub-channel ADCs. In spite of the advantages, this structure suffers from three mismatches, which are offset mismatch, gain mismatch, and time skew. This paper focuses on a TI SAR ADC with a number of channels. The mismatch effects in the frequency domain are analyzed and the derived close form formulas are verified based on Matlab. In addition, we clarify that the standard deviation of DNL and INL of an M-channel TI ADC is reduced by a factor of ~ compared to a single channel ADC. The formulas can be used to derive the corresponding requirements when designing a TI ADC. Our analysis process is able to inform the study of calibration algorithms.
文摘Recently, real-time simulation of renewable energy sources are indispensible for evaluating the performance of the maximum power point tracking （MPPT） controller, especially in the photovoltaic （PV） system in order to reduce cost in the testing phase. Nowadays, real time PV simulators are obtained by using analog and/or digital components. In this paper, a real-time simulation of a PV system with a boost converter was proposed using only the digital signal processor （DSP） processor with two DC voltage sources to emulate the temperature and irradiation in the PV system. A MATLAB/ Simulink environment was used to develop the real-time PV system with a boost converter into a C-program and build it into a DSP controller TMS320F28335. Besides, the performance of the real-time DSP-based PV was tested in different temperature and irradiation conditions to observe the P-V and V-I characteristics. Further, the performance of the PV with a boost converter was tested at different temperatures and irradiations using MPPT algorithms. This scheme was tested through simulation and the results were validated with that of standard conditions given in the PV data sheets. Implementation of this project helped to attract more researchers to study renewable energy applications without real sources. This might facilitate the study of PV systems in a real-time scenario and the evaluation of what should be expected for PV modules available in the market.
