This paper presents the design considerations and implementation of an area-efficient interpolator suitable for a delta-sigma D/A converter. In an effort to reduce the area and design complexity, a method for designin...This paper presents the design considerations and implementation of an area-efficient interpolator suitable for a delta-sigma D/A converter. In an effort to reduce the area and design complexity, a method for designing an FIR filter as a tapped cascaded interconnection of identical subfilters is modified. The proposed subfilter structure further minimizes the arithmetic number. Experimental results show that the proposed interpolator achieves the design specification,exhibiting high performance and hardware efficiency,and also has good noise rejection capability. The interpolation filter can be applied to a delta-sigma DAC and is fully functional.展开更多
A multi-standard compatible clock and data recovery circuit （CDR） with a programmable equalizer and wide tracking range is presented. Considering the jitter performance, tracking range and chip area, the CDR employs...A multi-standard compatible clock and data recovery circuit （CDR） with a programmable equalizer and wide tracking range is presented. Considering the jitter performance, tracking range and chip area, the CDR employs a first-order digital loop filter, two 6-bit DACs and high linearity phase interpolators to achieve high phase resolution and low area. Meanwhile the tracking range is greater than 4-2200 ppm, making this proposed CDR suitable for the embedded clock serial links. A test chip was fabricated in the 55 nm CMOS process. The measurements show that the test chip can achieve BER 〈 10^-12 and meet the jitter tolerance specification. The test chip occupies 0.19 mma with a 0.0486 mm^2 CDR core, which only consumes 30 mW from a 1.2 V supply at 5 Gb/s.展开更多
A two-step high-precision Time-to-Digital Converter(TDC),integrated with a Single-Photon Avalanche Diode(SPAD),used for Time-Of-Flight(TOF)application,has been developed and tested.Time interval measurement is perform...A two-step high-precision Time-to-Digital Converter(TDC),integrated with a Single-Photon Avalanche Diode(SPAD),used for Time-Of-Flight(TOF)application,has been developed and tested.Time interval measurement is performed by the coarse counter and fine interpolator,which are utilized to measure the total periods and the residue time of the reference clock,respectively.Following a detail analysis of time precision and clock jitter in the two-step structure,the prototype TDC fabricated in GSMC 1P6M 0.18μm CMOS Image Sensor(CIS)technology exhibits a Single-Shot Precision(SSP)of 11.415 ps and a dynamic range of 216.7 ns.In addition,a pixel of the chip occupies 100μm×100μm,and the measured Integral Nonlinearity(INL)and Differential Nonlinearity(DNL)are better than±0.88 LSB and±0.67 LSB,respectively.Meanwhile,the overall power consumption of the chip is 35 mW at 1.8 V power supply.Combined with these characteristics,the designed chip is suitable for TOF-based ranging applications.展开更多
A wide-range tracking technique for clock and data recovery(CDR) circuit is presented. Compared to the traditional technique, a digital CDR controller with calibration is adopted to extend the tracking range. Because ...A wide-range tracking technique for clock and data recovery(CDR) circuit is presented. Compared to the traditional technique, a digital CDR controller with calibration is adopted to extend the tracking range. Because of the use of digital circuits in the design, CDR is not sensitive to process and power supply variations. To verify the technique, the whole CDR circuit is implemented using 65-nm CMOS technology. Measurements show that the tracking range of CDR is greater than ±6×10-3 at 5 Gb/s. The receiver has good jitter tolerance performance and achieves a bit error rate of <10–12. The re-timed and re-multiplexed serial data has a root-mean-square jitter of 6.7 ps.展开更多
文摘This paper presents the design considerations and implementation of an area-efficient interpolator suitable for a delta-sigma D/A converter. In an effort to reduce the area and design complexity, a method for designing an FIR filter as a tapped cascaded interconnection of identical subfilters is modified. The proposed subfilter structure further minimizes the arithmetic number. Experimental results show that the proposed interpolator achieves the design specification,exhibiting high performance and hardware efficiency,and also has good noise rejection capability. The interpolation filter can be applied to a delta-sigma DAC and is fully functional.
基金Project supported by the National High Technology Research and Development Program of China(No.2011AA010403)the National Natural Science Foundation of China(No.61474134)the National Science and Technology Major Project(No.2014ZX02302002)
文摘A multi-standard compatible clock and data recovery circuit （CDR） with a programmable equalizer and wide tracking range is presented. Considering the jitter performance, tracking range and chip area, the CDR employs a first-order digital loop filter, two 6-bit DACs and high linearity phase interpolators to achieve high phase resolution and low area. Meanwhile the tracking range is greater than 4-2200 ppm, making this proposed CDR suitable for the embedded clock serial links. A test chip was fabricated in the 55 nm CMOS process. The measurements show that the test chip can achieve BER 〈 10^-12 and meet the jitter tolerance specification. The test chip occupies 0.19 mma with a 0.0486 mm^2 CDR core, which only consumes 30 mW from a 1.2 V supply at 5 Gb/s.
基金National Natural Science Foundation of China(61774129,61827812,61704145)Hunan Science and Technology Department Huxiang High-level Talent Gathering Project(2019RS1037)Changsha Science and Technology Plan Key Projects(kq1801035)。
文摘A two-step high-precision Time-to-Digital Converter(TDC),integrated with a Single-Photon Avalanche Diode(SPAD),used for Time-Of-Flight(TOF)application,has been developed and tested.Time interval measurement is performed by the coarse counter and fine interpolator,which are utilized to measure the total periods and the residue time of the reference clock,respectively.Following a detail analysis of time precision and clock jitter in the two-step structure,the prototype TDC fabricated in GSMC 1P6M 0.18μm CMOS Image Sensor(CIS)technology exhibits a Single-Shot Precision(SSP)of 11.415 ps and a dynamic range of 216.7 ns.In addition,a pixel of the chip occupies 100μm×100μm,and the measured Integral Nonlinearity(INL)and Differential Nonlinearity(DNL)are better than±0.88 LSB and±0.67 LSB,respectively.Meanwhile,the overall power consumption of the chip is 35 mW at 1.8 V power supply.Combined with these characteristics,the designed chip is suitable for TOF-based ranging applications.
基金Project supported by the National High-Tech R&D Program(863)of China(No.2011AA010403)the National Natural Science Foundation of China(No.61474134)
文摘A wide-range tracking technique for clock and data recovery(CDR) circuit is presented. Compared to the traditional technique, a digital CDR controller with calibration is adopted to extend the tracking range. Because of the use of digital circuits in the design, CDR is not sensitive to process and power supply variations. To verify the technique, the whole CDR circuit is implemented using 65-nm CMOS technology. Measurements show that the tracking range of CDR is greater than ±6×10-3 at 5 Gb/s. The receiver has good jitter tolerance performance and achieves a bit error rate of <10–12. The re-timed and re-multiplexed serial data has a root-mean-square jitter of 6.7 ps.
