如何在单相畸变电网中快速准确的获取基波以及所需的特定次谐波信息,对并网型电力电子变换器的控制系统而言是十分重要的。针对这一问题,提出了一种基于通用信号延迟叠加算子(generalized delayed signal superposition operator,GDSS)...如何在单相畸变电网中快速准确的获取基波以及所需的特定次谐波信息,对并网型电力电子变换器的控制系统而言是十分重要的。针对这一问题,提出了一种基于通用信号延迟叠加算子(generalized delayed signal superposition operator,GDSS)的单相锁相环结构,用于恶劣电网下系统基波以及多重谐波信息的检测。这种锁相环结构包含了多个具有很强频率选择特性的GDSS算子,能够在半个基波周期内从输入信号中分离出所需要的基波以及多个谐波频率信息,并且其参数以及GDSS算子个数还能够根据实际控制系统需求灵活调整。在各种工况下的仿真及实验表明,所提的锁相方法能够在恶劣电网下快速准确的获取基波及多重谐波信息,并且面对电网常见扰动时具有很强的鲁棒性。展开更多
It is very important to detect transition-delay faults and stuck-at faults in system on chip （SoC） under 90 nm processing technology, and the transition-delay faults can only be detected by using an at-speed testing...It is very important to detect transition-delay faults and stuck-at faults in system on chip （SoC） under 90 nm processing technology, and the transition-delay faults can only be detected by using an at-speed testing method. In this paper, an on-chip clock （OCC） controller with a bypass function based on an internal phase-locked loop is designed to test faults in SoC. Furthermore, a clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by automatic test pattern generation （ATPG） tools. Next, the scan test pattern is simulated by using the Synopsys tool and the correctness of the design is verified. The result shows that the design of an at-speed scan test in this paper is highly efficient for detecting timing-related defects. Finally, the 89.29% transition-delay fault coverage and the 94.50% stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design.展开更多
In this paper,a discrete-time analysis of the third-order charge-pump based phase-locked loops (CPLLs) is presented in the presence of loop delay.The z-domain analysis of the closed-loop transfer function is derived a...In this paper,a discrete-time analysis of the third-order charge-pump based phase-locked loops (CPLLs) is presented in the presence of loop delay.The z-domain analysis of the closed-loop transfer function is derived and compared with the traditional s-domain method.The simulation results under SPECTRE show that,due to the sampling nature of CPLL,the traditional s-domain analysis is unable to predict its jitter peaking accurately,especially when the loop delay is taken into consideration.The impact of loop delay on the stability of the third-order CPLL system is further analyzed based on the proposed way.The stability limit of the wide bandwidth CPLL with loop delay is calculated.The circuit simulation results agree well with mathematical analysis.展开更多
Phase-locked loops (PLLs) are essential wherever a local event is synchronized with a periodic external event. They are utilized as on-chip clock frequency generators to synthesize a low skew and higher internal frequ...Phase-locked loops (PLLs) are essential wherever a local event is synchronized with a periodic external event. They are utilized as on-chip clock frequency generators to synthesize a low skew and higher internal frequency clock from an external lower frequency signal and its characterization and measurement have recently been calling for more and more attention. In this paper, a built-in on-chip circuit for measuring jitter of PLL based on a duty cycle modulation vernier delay line is proposed and demonstrated. The circuit employs two delay lines to measure the timing difference and transform the difference signal into digital words. The vernier lines are composed of delay cells whose duty cycle can be adjusted by a feedback voltage. It enables the circuit to have a self calibration capability which eliminates the mismatch problem caused by the process variation.展开更多
文摘如何在单相畸变电网中快速准确的获取基波以及所需的特定次谐波信息,对并网型电力电子变换器的控制系统而言是十分重要的。针对这一问题,提出了一种基于通用信号延迟叠加算子(generalized delayed signal superposition operator,GDSS)的单相锁相环结构,用于恶劣电网下系统基波以及多重谐波信息的检测。这种锁相环结构包含了多个具有很强频率选择特性的GDSS算子,能够在半个基波周期内从输入信号中分离出所需要的基波以及多个谐波频率信息,并且其参数以及GDSS算子个数还能够根据实际控制系统需求灵活调整。在各种工况下的仿真及实验表明,所提的锁相方法能够在恶劣电网下快速准确的获取基波及多重谐波信息,并且面对电网常见扰动时具有很强的鲁棒性。
基金Project supported by the Key Project Science and Technology Cooperation of Fujian Province,China(No.2013I0003)
文摘It is very important to detect transition-delay faults and stuck-at faults in system on chip （SoC） under 90 nm processing technology, and the transition-delay faults can only be detected by using an at-speed testing method. In this paper, an on-chip clock （OCC） controller with a bypass function based on an internal phase-locked loop is designed to test faults in SoC. Furthermore, a clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by automatic test pattern generation （ATPG） tools. Next, the scan test pattern is simulated by using the Synopsys tool and the correctness of the design is verified. The result shows that the design of an at-speed scan test in this paper is highly efficient for detecting timing-related defects. Finally, the 89.29% transition-delay fault coverage and the 94.50% stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design.
基金Supported by National Natural Science Foundation of China(No.61204028)
文摘In this paper,a discrete-time analysis of the third-order charge-pump based phase-locked loops (CPLLs) is presented in the presence of loop delay.The z-domain analysis of the closed-loop transfer function is derived and compared with the traditional s-domain method.The simulation results under SPECTRE show that,due to the sampling nature of CPLL,the traditional s-domain analysis is unable to predict its jitter peaking accurately,especially when the loop delay is taken into consideration.The impact of loop delay on the stability of the third-order CPLL system is further analyzed based on the proposed way.The stability limit of the wide bandwidth CPLL with loop delay is calculated.The circuit simulation results agree well with mathematical analysis.
文摘Phase-locked loops (PLLs) are essential wherever a local event is synchronized with a periodic external event. They are utilized as on-chip clock frequency generators to synthesize a low skew and higher internal frequency clock from an external lower frequency signal and its characterization and measurement have recently been calling for more and more attention. In this paper, a built-in on-chip circuit for measuring jitter of PLL based on a duty cycle modulation vernier delay line is proposed and demonstrated. The circuit employs two delay lines to measure the timing difference and transform the difference signal into digital words. The vernier lines are composed of delay cells whose duty cycle can be adjusted by a feedback voltage. It enables the circuit to have a self calibration capability which eliminates the mismatch problem caused by the process variation.
