Delay considerttion has been a major issue in design and test of high performance digital circuits . The assumption of input signal change occurring only when all internal nodes are stable restricts the increase of cl...Delay considerttion has been a major issue in design and test of high performance digital circuits . The assumption of input signal change occurring only when all internal nodes are stable restricts the increase of clock frequency. It is no longer true for wave pipelining circuits. However, previous logical delay models are based on the assumption. In addition, the stable time of a robust delay test generally depends on the longest sensitizable path delay. Thus , a new delay model is desirable. This paper explores the necessity first. Then, Boolean process to analytically describe the logical and timing behavior of a digital circuit is reviewed . The concept of sensitization is redefined precisely in this paper. Based on the new concept of sensitization, an analytical delay model is introduced . As a result , many untestable delay faults under the logical delay model can be tested if the output waveforms can be sampled at more time points. The longest sensitiaable path length is computed for circuit design and delay test .展开更多
文摘Delay considerttion has been a major issue in design and test of high performance digital circuits . The assumption of input signal change occurring only when all internal nodes are stable restricts the increase of clock frequency. It is no longer true for wave pipelining circuits. However, previous logical delay models are based on the assumption. In addition, the stable time of a robust delay test generally depends on the longest sensitizable path delay. Thus , a new delay model is desirable. This paper explores the necessity first. Then, Boolean process to analytically describe the logical and timing behavior of a digital circuit is reviewed . The concept of sensitization is redefined precisely in this paper. Based on the new concept of sensitization, an analytical delay model is introduced . As a result , many untestable delay faults under the logical delay model can be tested if the output waveforms can be sampled at more time points. The longest sensitiaable path length is computed for circuit design and delay test .
