存内计算(Computing In Memory,CIM)在人工智能神经网络的卷积运算方面具有巨大的应用潜力。基于忆阻器阵列的多位存内计算由于具备写入速度快、与互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)工艺兼容等特点,...存内计算(Computing In Memory,CIM)在人工智能神经网络的卷积运算方面具有巨大的应用潜力。基于忆阻器阵列的多位存内计算由于具备写入速度快、与互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)工艺兼容等特点,有望成为解决“内存墙”的有效手段。然而,当前多位存内计算电路架构面临输出延时高和能耗大的问题,主要原因为传统感知放大器的性能制约,为此本文提出了一种低延时低能耗多位电流型感知放大器(Low-delay Low-power Multi-bit Current-mode Sense Amplifier,LLM-CSA),通过减少传统CSA电路工作状态数量、简化工作时序来优化功能;采用新型低位检测模块的电路设计思路,来多层次系统性地降低输出延时并优化能耗。使用中芯国际40 nm低漏电逻辑工艺(SMIC40 nm LL),利用Cadence电路设计平台,仿真验证所提LLM-CSA的功能和延时-能耗性能。通过对比分析发现:LLM-CSA比传统CSA输出延时降低1.42倍,能量消耗降低1.56倍。进一步地,以一种4 bit输入、4 bit权重、11 bit输出的忆阻器阵列多位存内计算架构为应用,对比验证所提LLM-CSA的性能:与基于传统CSA的存内计算系统相比,新架构延时降低1.18倍,能耗降低1.03倍。LLM-CSA的提出对促进感知放大器设计思路和忆阻器阵列存内计算架构的发展,具有一定的理论和现实意义。展开更多
基于0.5μm BCD工艺,设计了一种用于低边电流检测的可编程增益放大器(Programmable Gain Amplifier,PGA)。采用了电流模闭环可编程增益放大器结构,将传统电压模反馈电阻网络对采样电路的漏电流影响减小到纳安级别。设计了一种全差分高...基于0.5μm BCD工艺,设计了一种用于低边电流检测的可编程增益放大器(Programmable Gain Amplifier,PGA)。采用了电流模闭环可编程增益放大器结构,将传统电压模反馈电阻网络对采样电路的漏电流影响减小到纳安级别。设计了一种全差分高精度可变跨导放大器,给PGA提供了更加精准的可变增益。仿真结果表明,PGA放大倍数为4时,测量误差为0.2%,PGA放大倍数为256时,测量误差为3.11%,总谐波失真小于0.021%,芯片面积为1.5 mm×1.5 mm。展开更多
A novel asymmetrical current-based sensing scheme for 1T1C FRAM is proposed,in which the two input transistors are not the same size and a feedback NMOS is added at the reference side of the sense amplifier.Compared w...A novel asymmetrical current-based sensing scheme for 1T1C FRAM is proposed,in which the two input transistors are not the same size and a feedback NMOS is added at the reference side of the sense amplifier.Compared with the conventional symmetrical scheme in Ref.[8],the proposed scheme increases the sense margin of the readout current by 53.9%and decreases the sensing power consumption by 14.1%,at the cost of an additional 7.89%area of the sensing scheme.An experimental FRAM prototype utilizing the proposed asymmetrical scheme is implemented in a 0.35μm three metal process,in which the function of the prototype is verified.展开更多
基金Project supported by the National High Technology Research and Development Program of China(No.2009AA01Z115)the Key National Science and Technology Specific Project of China(No.2009ZX02023-1-3)
文摘A novel asymmetrical current-based sensing scheme for 1T1C FRAM is proposed,in which the two input transistors are not the same size and a feedback NMOS is added at the reference side of the sense amplifier.Compared with the conventional symmetrical scheme in Ref.[8],the proposed scheme increases the sense margin of the readout current by 53.9%and decreases the sensing power consumption by 14.1%,at the cost of an additional 7.89%area of the sensing scheme.An experimental FRAM prototype utilizing the proposed asymmetrical scheme is implemented in a 0.35μm three metal process,in which the function of the prototype is verified.
