The main objective of this paper is three-fold.First, to provide an overview of the current status of the power electronics technology, one of the key actors in the upcoming smart grid paradigm enabling maximum power ...The main objective of this paper is three-fold.First, to provide an overview of the current status of the power electronics technology, one of the key actors in the upcoming smart grid paradigm enabling maximum power throughputs and near-instantaneous control of voltages and currents in all links of the power system chain. Second, to provide a bridge between the power systems and the power electronic communities, in terms of their differing appreciation of how these devices perform when connected to the power grid. Third, to discuss on the role that the power electronics technology will play in supporting the aims and objectives of future decarbonized power systems. This paper merges the equipment, control techniques and methods used in flexible alternating current transmission systems(FACTS) and high voltage direct transmission(HVDC) equipment to enable a single, coherent approach to address a specific power system problem, using ‘best of breed’ solutions bearing in mind technical, economic and environmental issues.展开更多
The relationship between A1GaN/GaN HEMT gate field plate （FP） and surface-state-related gate lag phenomena is investigated by two-dimensional numerical transient simulations to study the mechanism of the influence o...The relationship between A1GaN/GaN HEMT gate field plate （FP） and surface-state-related gate lag phenomena is investigated by two-dimensional numerical transient simulations to study the mechanism of the influence of FPs on current collapse. The simulations reveal that adding a field plate has a noticeable impact on the extent of current collapse while it has no influence on lapsed time. The FP is found to suppress current collapse through reducing the ionization probability of surface states by enhancing free hole accumulation next to the AIGaN surface between gate and drain.展开更多
A direct tunneling model through gate dielectric s in CMOS devices in the frame of WKB approximation is reported.In the model,an im proved one-band effective mass approximation is used for the hole quantization, wher...A direct tunneling model through gate dielectric s in CMOS devices in the frame of WKB approximation is reported.In the model,an im proved one-band effective mass approximation is used for the hole quantization, where valence band mixing is taken into account.By comparing to the experiments, the model is demonstrated to be applicable to both electron and hole tunneling c urrents in CMOS devices.The effect of the dispersion in oxide energy gap on the tunneling current is also studied.This model can be further extended to study th e direct tunneling current in future high-k materials.展开更多
本文研究了0.8μm SOI NMOS晶体管,经剂量率为50rad(Si)/s的60Coγ射线辐照之后的总剂量效应,分析了器件在不同辐照条件和测量偏置下的辐照响应特性.研究结果表明:器件辐照时的栅偏置电压越高,辐照后栅氧化层中积累的空穴陷阱电荷越多,...本文研究了0.8μm SOI NMOS晶体管,经剂量率为50rad(Si)/s的60Coγ射线辐照之后的总剂量效应,分析了器件在不同辐照条件和测量偏置下的辐照响应特性.研究结果表明:器件辐照时的栅偏置电压越高,辐照后栅氧化层中积累的空穴陷阱电荷越多,引起的漏极泄漏电流越大.对于漏偏置为5V的器件,当栅电压大于阈值电压时,前栅ID-VG特性曲线中的漏极电流因碰撞电离而突然增大,体电极的电流曲线呈现倒立的钟形.展开更多
High-voltage controller area network(CAN)buses have a harsh working environment and require a robust electrostatic discharge(ESD)design window.Thus,ordinary silicon-controlled rectifier(SCR)devices do not satisfy thes...High-voltage controller area network(CAN)buses have a harsh working environment and require a robust electrostatic discharge(ESD)design window.Thus,ordinary silicon-controlled rectifier(SCR)devices do not satisfy these design requirements.To streamline the design and manufacturing of SCRs,this study proposes a novel dual-gate dual-direction SCR(DG-DDSCR)with a high failure current and holding voltage.First,four polysilicon gates,GateA1,GateA2,GateC1,and GateC2,were introduced to the N+and P+middle regions of the anode and cathode.When the voltage acts on the anode,the electric field generated by the polysilicon gate strengthens the SCR current path while promoting the release of ESD current in the substrate path.Specifically,the holding voltage of the DG-DDSCR and failure current derived from the test results of a transmission line pulse(TLP)are 29.4 V and 16.7 A,respectively.When the clamping voltage was 40 V,the transient current release of the structure can reach 11.61 A,which met the specifications of the CAN bus ESD window and was suitable for the ESD protection of the target application.展开更多
AlGaN/GaN high electron mobility transistors（HEMTs）with high performance were fabricated and characterized.A variety of techniques were used to improve device performance,such as AlN interlayer,silicon nitride passi...AlGaN/GaN high electron mobility transistors（HEMTs）with high performance were fabricated and characterized.A variety of techniques were used to improve device performance,such as AlN interlayer,silicon nitride passivation,high aspect ratio T-shaped gate,low resistance ohmic contact and short drain-source distance. DC and RF performances of as-fabricated HEMTs were characterized by utilizing a semiconductor characterization system and a vector network analyzer,respectively.As-fabricated devices exhibited a maximum drain current density of 1.41 A/mm and a maximum peak extrinsic transconductance of 317 mS/mm.The obtained current density is larger than those reported in the literature to date,implemented with a domestic wafer and processes.Furthermore, a unity current gain cut-off frequency of 74.3 GHz and a maximum oscillation frequency of 112.4 GHz were obtained on a device with an 80 nm gate length.展开更多
The MOSFET gate currents of high k gate dielectrics due to direct tunneling are investigated by using a new direct tunneling current model developed.The model includes both the inversion layer quantization effect with...The MOSFET gate currents of high k gate dielectrics due to direct tunneling are investigated by using a new direct tunneling current model developed.The model includes both the inversion layer quantization effect with finite barrier height and the polysilicon depletion effect.The impacts of dielectric constant and conduction band offset as well as the band gap on the gate current are discussed.The results indicate that the gate dielectric materials with higher dielectric constant,larger conduction band offset and the larger band gap are necessary to reduce the gate current.The calculated results can be used as a guide to select the appropriate high k gate dielectric materials for MOSFETs.展开更多
Silicon on insulator (SOI) technology permits a good solution to the miniaturization as the MOSFET size scales down. This paper is about to compare the electrical performance of nanoscale FD-SOI MOSFET at various gate...Silicon on insulator (SOI) technology permits a good solution to the miniaturization as the MOSFET size scales down. This paper is about to compare the electrical performance of nanoscale FD-SOI MOSFET at various gate lengths. The performance is compared and contrasted with the help of threshold voltage, subthreshold slope, on-state current and leakage current. Interestingly, by decreasing the gate length, the leakage current and on-state current are increased but the threshold voltage is decreased and the sub-threshold slope is degraded. Silvaco two-dimensional simulations are used to analyze the performance of the proposed structures.展开更多
lnA1N/GaN high-electron-mobility transistors （HEMTs） on SiC substrate were fabricated and character- ized. Several techniques, consisting of high electron density, 70 nm T-shaped gate, low ohmic contacts and a short...lnA1N/GaN high-electron-mobility transistors （HEMTs） on SiC substrate were fabricated and character- ized. Several techniques, consisting of high electron density, 70 nm T-shaped gate, low ohmic contacts and a short drain-source distance, are integrated to gain high device performance. The fabricated InA1N/GaN HEMTs exhibit a maximum drain saturation current density of 1.65 A/ram at Vgs = 1 V and a maximum peak transconductance of 382 mS/rnm. In addition, a unity current gain cut-off frequency （fT） of 162 GHz and a maximum oscillation frequency （fmax） of 176 GHz are achieved on the devices with the 70 nm gate length.展开更多
We fabricated a set of symmetric gate-recess devices with gate length of 70 nm.We kept the source-to-drain spacing(L_(SD))unchanged,and obtained a group of devices with gate-recess length(L_(recess))from 0.4µm to...We fabricated a set of symmetric gate-recess devices with gate length of 70 nm.We kept the source-to-drain spacing(L_(SD))unchanged,and obtained a group of devices with gate-recess length(L_(recess))from 0.4µm to 0.8µm through process improvement.In order to suppress the influence of the kink effect,we have done SiN_(X) passivation treatment.The maximum saturation current density(ID_(max))and maximum transconductance(g_(m,max))increase as L_(recess) decreases to 0.4µm.At this time,the device shows ID_(max)=749.6 mA/mm at V_(GS)=0.2 V,V_(DS)=1.5 V,and g_(m,max)=1111 mS/mm at V_(GS)=−0.35 V,V_(DS)=1.5 V.Meanwhile,as L_(recess) increases,it causes parasitic capacitance C_(gd) and g_(d) to decrease,making f_(max) drastically increases.When L_(recess)=0.8µm,the device shows f_(T)=188 GHz and f_(max)=1112 GHz.展开更多
The reverse generation current under high-gate-voltage stress condition in LDD nMOSFET＇s is studied. We find that the generation current peak decreases as the stress time increases. We ascribe this finding to the dom...The reverse generation current under high-gate-voltage stress condition in LDD nMOSFET＇s is studied. We find that the generation current peak decreases as the stress time increases. We ascribe this finding to the dominating oxide trapped electrons that reduce the effective drain bias, lowering the maximal generation rate. The density of the effective trapped electrons affecting the effective drain bias is calculated with our model.展开更多
Dual-metal gate and gate–drain underlap designs are introduced to reduce the ambipolar current of the device based on the C-shaped pocket TFET(CSP-TFET).The effects of gate work function and gate–drain underlap leng...Dual-metal gate and gate–drain underlap designs are introduced to reduce the ambipolar current of the device based on the C-shaped pocket TFET(CSP-TFET).The effects of gate work function and gate–drain underlap length on the DC characteristics and analog/RF performance of CSP-TFET devices,such as the on-state current(I_(on)),ambipolar current(I_(amb)),transconductance(g_(m)),cut-off frequency(f_(T))and gain–bandwidth product(GBP),are analyzed and compared in this work.Also,a combination of both the dual-metal gate and gate–drain underlap designs has been proposed for the C-shaped pocket dual metal underlap TFET(CSP-DMUN-TFET),which contains a C-shaped pocket area that significantly increases the on-state current of the device;this combination design substantially reduces the ambipolar current.The results show that the CSP-DMUN-TFET demonstrates an excellent performance,including high I_(on)(9.03×10^(-4)A/μm),high I_(on)/I_(off)(~10^(11)),low SS_(avg)(~13 mV/dec),and low I_(amb)(2.15×10^(-17)A/μm).The CSP-DMUN-TFET has the capability to fully suppress ambipolar currents while maintaining high on-state currents,making it a potential replacement in the next generation of semiconductor devices.展开更多
基金supported by Spanish Ministry of Economy and Competitiveness and Junta de Andalucía through the projects ENE2014-54115-R and TEP-7411
文摘The main objective of this paper is three-fold.First, to provide an overview of the current status of the power electronics technology, one of the key actors in the upcoming smart grid paradigm enabling maximum power throughputs and near-instantaneous control of voltages and currents in all links of the power system chain. Second, to provide a bridge between the power systems and the power electronic communities, in terms of their differing appreciation of how these devices perform when connected to the power grid. Third, to discuss on the role that the power electronics technology will play in supporting the aims and objectives of future decarbonized power systems. This paper merges the equipment, control techniques and methods used in flexible alternating current transmission systems(FACTS) and high voltage direct transmission(HVDC) equipment to enable a single, coherent approach to address a specific power system problem, using ‘best of breed’ solutions bearing in mind technical, economic and environmental issues.
文摘The relationship between A1GaN/GaN HEMT gate field plate （FP） and surface-state-related gate lag phenomena is investigated by two-dimensional numerical transient simulations to study the mechanism of the influence of FPs on current collapse. The simulations reveal that adding a field plate has a noticeable impact on the extent of current collapse while it has no influence on lapsed time. The FP is found to suppress current collapse through reducing the ionization probability of surface states by enhancing free hole accumulation next to the AIGaN surface between gate and drain.
文摘A direct tunneling model through gate dielectric s in CMOS devices in the frame of WKB approximation is reported.In the model,an im proved one-band effective mass approximation is used for the hole quantization, where valence band mixing is taken into account.By comparing to the experiments, the model is demonstrated to be applicable to both electron and hole tunneling c urrents in CMOS devices.The effect of the dispersion in oxide energy gap on the tunneling current is also studied.This model can be further extended to study th e direct tunneling current in future high-k materials.
文摘本文研究了0.8μm SOI NMOS晶体管,经剂量率为50rad(Si)/s的60Coγ射线辐照之后的总剂量效应,分析了器件在不同辐照条件和测量偏置下的辐照响应特性.研究结果表明:器件辐照时的栅偏置电压越高,辐照后栅氧化层中积累的空穴陷阱电荷越多,引起的漏极泄漏电流越大.对于漏偏置为5V的器件,当栅电压大于阈值电压时,前栅ID-VG特性曲线中的漏极电流因碰撞电离而突然增大,体电极的电流曲线呈现倒立的钟形.
基金National Natural Science Foundation of China(62174052).
文摘High-voltage controller area network(CAN)buses have a harsh working environment and require a robust electrostatic discharge(ESD)design window.Thus,ordinary silicon-controlled rectifier(SCR)devices do not satisfy these design requirements.To streamline the design and manufacturing of SCRs,this study proposes a novel dual-gate dual-direction SCR(DG-DDSCR)with a high failure current and holding voltage.First,four polysilicon gates,GateA1,GateA2,GateC1,and GateC2,were introduced to the N+and P+middle regions of the anode and cathode.When the voltage acts on the anode,the electric field generated by the polysilicon gate strengthens the SCR current path while promoting the release of ESD current in the substrate path.Specifically,the holding voltage of the DG-DDSCR and failure current derived from the test results of a transmission line pulse(TLP)are 29.4 V and 16.7 A,respectively.When the clamping voltage was 40 V,the transient current release of the structure can reach 11.61 A,which met the specifications of the CAN bus ESD window and was suitable for the ESD protection of the target application.
文摘AlGaN/GaN high electron mobility transistors（HEMTs）with high performance were fabricated and characterized.A variety of techniques were used to improve device performance,such as AlN interlayer,silicon nitride passivation,high aspect ratio T-shaped gate,low resistance ohmic contact and short drain-source distance. DC and RF performances of as-fabricated HEMTs were characterized by utilizing a semiconductor characterization system and a vector network analyzer,respectively.As-fabricated devices exhibited a maximum drain current density of 1.41 A/mm and a maximum peak extrinsic transconductance of 317 mS/mm.The obtained current density is larger than those reported in the literature to date,implemented with a domestic wafer and processes.Furthermore, a unity current gain cut-off frequency of 74.3 GHz and a maximum oscillation frequency of 112.4 GHz were obtained on a device with an 80 nm gate length.
文摘The MOSFET gate currents of high k gate dielectrics due to direct tunneling are investigated by using a new direct tunneling current model developed.The model includes both the inversion layer quantization effect with finite barrier height and the polysilicon depletion effect.The impacts of dielectric constant and conduction band offset as well as the band gap on the gate current are discussed.The results indicate that the gate dielectric materials with higher dielectric constant,larger conduction band offset and the larger band gap are necessary to reduce the gate current.The calculated results can be used as a guide to select the appropriate high k gate dielectric materials for MOSFETs.
文摘Silicon on insulator (SOI) technology permits a good solution to the miniaturization as the MOSFET size scales down. This paper is about to compare the electrical performance of nanoscale FD-SOI MOSFET at various gate lengths. The performance is compared and contrasted with the help of threshold voltage, subthreshold slope, on-state current and leakage current. Interestingly, by decreasing the gate length, the leakage current and on-state current are increased but the threshold voltage is decreased and the sub-threshold slope is degraded. Silvaco two-dimensional simulations are used to analyze the performance of the proposed structures.
基金supported by the National Natural Science Foundation of China(No.61306113)
文摘lnA1N/GaN high-electron-mobility transistors （HEMTs） on SiC substrate were fabricated and character- ized. Several techniques, consisting of high electron density, 70 nm T-shaped gate, low ohmic contacts and a short drain-source distance, are integrated to gain high device performance. The fabricated InA1N/GaN HEMTs exhibit a maximum drain saturation current density of 1.65 A/ram at Vgs = 1 V and a maximum peak transconductance of 382 mS/rnm. In addition, a unity current gain cut-off frequency （fT） of 162 GHz and a maximum oscillation frequency （fmax） of 176 GHz are achieved on the devices with the 70 nm gate length.
基金the National Natural Science Foundation of China(Grant No.61434006).
文摘We fabricated a set of symmetric gate-recess devices with gate length of 70 nm.We kept the source-to-drain spacing(L_(SD))unchanged,and obtained a group of devices with gate-recess length(L_(recess))from 0.4µm to 0.8µm through process improvement.In order to suppress the influence of the kink effect,we have done SiN_(X) passivation treatment.The maximum saturation current density(ID_(max))and maximum transconductance(g_(m,max))increase as L_(recess) decreases to 0.4µm.At this time,the device shows ID_(max)=749.6 mA/mm at V_(GS)=0.2 V,V_(DS)=1.5 V,and g_(m,max)=1111 mS/mm at V_(GS)=−0.35 V,V_(DS)=1.5 V.Meanwhile,as L_(recess) increases,it causes parasitic capacitance C_(gd) and g_(d) to decrease,making f_(max) drastically increases.When L_(recess)=0.8µm,the device shows f_(T)=188 GHz and f_(max)=1112 GHz.
文摘The reverse generation current under high-gate-voltage stress condition in LDD nMOSFET＇s is studied. We find that the generation current peak decreases as the stress time increases. We ascribe this finding to the dominating oxide trapped electrons that reduce the effective drain bias, lowering the maximal generation rate. The density of the effective trapped electrons affecting the effective drain bias is calculated with our model.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.52177185 and 62174055)。
文摘Dual-metal gate and gate–drain underlap designs are introduced to reduce the ambipolar current of the device based on the C-shaped pocket TFET(CSP-TFET).The effects of gate work function and gate–drain underlap length on the DC characteristics and analog/RF performance of CSP-TFET devices,such as the on-state current(I_(on)),ambipolar current(I_(amb)),transconductance(g_(m)),cut-off frequency(f_(T))and gain–bandwidth product(GBP),are analyzed and compared in this work.Also,a combination of both the dual-metal gate and gate–drain underlap designs has been proposed for the C-shaped pocket dual metal underlap TFET(CSP-DMUN-TFET),which contains a C-shaped pocket area that significantly increases the on-state current of the device;this combination design substantially reduces the ambipolar current.The results show that the CSP-DMUN-TFET demonstrates an excellent performance,including high I_(on)(9.03×10^(-4)A/μm),high I_(on)/I_(off)(~10^(11)),low SS_(avg)(~13 mV/dec),and low I_(amb)(2.15×10^(-17)A/μm).The CSP-DMUN-TFET has the capability to fully suppress ambipolar currents while maintaining high on-state currents,making it a potential replacement in the next generation of semiconductor devices.
