In present era, one of the most important resources of computer machine is CPU. With the increasing number of application, there exist a large number of processes in the computer system at the same time. Many processe...In present era, one of the most important resources of computer machine is CPU. With the increasing number of application, there exist a large number of processes in the computer system at the same time. Many processes in system simultaneously raise a challenging circumstance of managing the CPU in such a manner that the CPU utilization and processes execution gets optimal performance. The world is still waiting for most efficient algorithm which remains a challenging issue. In this manuscript, we have proposed a new algorithm Progressively Varying Response Ratio Priority a preemptive CPU scheduling algorithm based on the Priority Algorithm and Shortest Remaining Time First. In this scheduling algorithm, the priority is been calculated and the processes with high priority get CPU first or next. For new process, the priority of it becomes equal to inverse of burst time and for the old processes the priority calculation takes place as a ratio of waiting time and remaining burst time. The objective is to get all the processes executed with minimum average waiting time and no starvation. Experiment and comparison show that the VRRP outperforms other CPU scheduling algorithms. It gives better evaluation results in the form of scheduling criteria. We have used the deterministic model to compare the different algorithms.展开更多
The performance of scalable shared-memory multiprocessors suffers from three types of latency; memory latency, the latency caused by inter-process synchronization ,and the latency caused by instructions that take mult...The performance of scalable shared-memory multiprocessors suffers from three types of latency; memory latency, the latency caused by inter-process synchronization ,and the latency caused by instructions that take multiple cycles to produce results To tolerate these three types of latencies, The following techniques was proposed to couple: coarse-grained multithreading, the superscalar processor and a reconfigurable device, namely the overlapping long latency operations of one thread of computation with the execution of other threads The superscalar processor principle is used to tolerate instruction latency by issuing several instructions simultaneously The DPGA is coupled with this processor in order to improve the context-switching展开更多
The paper will discuss the process of code-switching and its cognitive pragmatic motivation from the point of relevance.And code-switching is also regarded as a kind of communicative strategy.The process of the produc...The paper will discuss the process of code-switching and its cognitive pragmatic motivation from the point of relevance.And code-switching is also regarded as a kind of communicative strategy.The process of the production of code-switching is also the cooperation and mutual constrain of communicator’s cognitive environment and ability.Cognitive effect can be obtained through communicator’s processing cognitive environment with their cognitive ability.In this process,the cooperation of cognitive ability and cognitive environment gives a guarantee to successful communication with code-switching.展开更多
In this study, we present a miniOS kernel implemented via analysis of the context switching, the scheduler, and the memory management of the original OS kernel for an embedded system based on ARM core. Since this is a...In this study, we present a miniOS kernel implemented via analysis of the context switching, the scheduler, and the memory management of the original OS kernel for an embedded system based on ARM core. Since this is a large subject, we have limited our scope to them only that made up an embedded operating system. The implemented miniOS kernel is composed only by them, to the exclusion of all other functions of the original kernel. Our goal is to modify the OS kernel depending on the product function. The implementation method of the miniOS kernel can be applicable to any OS being mounted based on the ARM core. Modifying the kernel depending on the product function can improve the OS booting speed as well as save the system memory. The functions of the scheduler, the context switching, and the memory management are described with the source in each section. The miniOS kernel was implemented in the Assembly and C language and was verified through the build and the test. The results are shown in the Section 5.展开更多
With recent efforts to build foundational certified software systems, two different approaches have been proposed to certify thread context switching. One is to certify both threads and context switching in a single l...With recent efforts to build foundational certified software systems, two different approaches have been proposed to certify thread context switching. One is to certify both threads and context switching in a single logic system, and the other certifies threads and context switching at different abstraction levels. The former requires heavyweight extensions in the logic system to support first-class code pointers and recursive specifications. Moreover, the specification for context switching is very complex. The latter supports simpler and more natural specifications, but it requires the contexts of threads to be abstracted away completely when threads are certified. As a result, the conventional implementation of context switching used in most systems needs to be revised to make the abstraction work. In this paper, we extend the second approach to certify the conventional implementation, where the clear abstraction for threads is unavailable since both threads and context switching hold pointers of thread contexts. To solve this problem, we allow the program specifications for threads to refer to pointers of thread contexts. Thread contexts are treated as opaque structures, whose contents are unspecified and should never be accessed by the code of threads. Therefore, the advantage of avoiding the direct support of first-class code pointers is still preserved in our method. Besides, our new approach is also more lightweight. Instead of using two different logics to certify threads and context switching, we employ only one program logic with two different specifications for the context switching. One is used to certify the implementation itself, and the more abstract one is used as an interface between threads and context switching at a higher abstraction level. The consistency between the two specifications are enforced by the global program invariant.展开更多
文摘In present era, one of the most important resources of computer machine is CPU. With the increasing number of application, there exist a large number of processes in the computer system at the same time. Many processes in system simultaneously raise a challenging circumstance of managing the CPU in such a manner that the CPU utilization and processes execution gets optimal performance. The world is still waiting for most efficient algorithm which remains a challenging issue. In this manuscript, we have proposed a new algorithm Progressively Varying Response Ratio Priority a preemptive CPU scheduling algorithm based on the Priority Algorithm and Shortest Remaining Time First. In this scheduling algorithm, the priority is been calculated and the processes with high priority get CPU first or next. For new process, the priority of it becomes equal to inverse of burst time and for the old processes the priority calculation takes place as a ratio of waiting time and remaining burst time. The objective is to get all the processes executed with minimum average waiting time and no starvation. Experiment and comparison show that the VRRP outperforms other CPU scheduling algorithms. It gives better evaluation results in the form of scheduling criteria. We have used the deterministic model to compare the different algorithms.
文摘The performance of scalable shared-memory multiprocessors suffers from three types of latency; memory latency, the latency caused by inter-process synchronization ,and the latency caused by instructions that take multiple cycles to produce results To tolerate these three types of latencies, The following techniques was proposed to couple: coarse-grained multithreading, the superscalar processor and a reconfigurable device, namely the overlapping long latency operations of one thread of computation with the execution of other threads The superscalar processor principle is used to tolerate instruction latency by issuing several instructions simultaneously The DPGA is coupled with this processor in order to improve the context-switching
文摘The paper will discuss the process of code-switching and its cognitive pragmatic motivation from the point of relevance.And code-switching is also regarded as a kind of communicative strategy.The process of the production of code-switching is also the cooperation and mutual constrain of communicator’s cognitive environment and ability.Cognitive effect can be obtained through communicator’s processing cognitive environment with their cognitive ability.In this process,the cooperation of cognitive ability and cognitive environment gives a guarantee to successful communication with code-switching.
文摘In this study, we present a miniOS kernel implemented via analysis of the context switching, the scheduler, and the memory management of the original OS kernel for an embedded system based on ARM core. Since this is a large subject, we have limited our scope to them only that made up an embedded operating system. The implemented miniOS kernel is composed only by them, to the exclusion of all other functions of the original kernel. Our goal is to modify the OS kernel depending on the product function. The implementation method of the miniOS kernel can be applicable to any OS being mounted based on the ARM core. Modifying the kernel depending on the product function can improve the OS booting speed as well as save the system memory. The functions of the scheduler, the context switching, and the memory management are described with the source in each section. The miniOS kernel was implemented in the Assembly and C language and was verified through the build and the test. The results are shown in the Section 5.
基金Supported by the National Natural Science Foundation of China under Grant Nos.90718026 and 60928004,ChinaPostdoctoral Science Foundation under Grant No.20080430770Natural Science Foundation of Jiangsu Province,China under Grant No. BK2008181
文摘With recent efforts to build foundational certified software systems, two different approaches have been proposed to certify thread context switching. One is to certify both threads and context switching in a single logic system, and the other certifies threads and context switching at different abstraction levels. The former requires heavyweight extensions in the logic system to support first-class code pointers and recursive specifications. Moreover, the specification for context switching is very complex. The latter supports simpler and more natural specifications, but it requires the contexts of threads to be abstracted away completely when threads are certified. As a result, the conventional implementation of context switching used in most systems needs to be revised to make the abstraction work. In this paper, we extend the second approach to certify the conventional implementation, where the clear abstraction for threads is unavailable since both threads and context switching hold pointers of thread contexts. To solve this problem, we allow the program specifications for threads to refer to pointers of thread contexts. Thread contexts are treated as opaque structures, whose contents are unspecified and should never be accessed by the code of threads. Therefore, the advantage of avoiding the direct support of first-class code pointers is still preserved in our method. Besides, our new approach is also more lightweight. Instead of using two different logics to certify threads and context switching, we employ only one program logic with two different specifications for the context switching. One is used to certify the implementation itself, and the more abstract one is used as an interface between threads and context switching at a higher abstraction level. The consistency between the two specifications are enforced by the global program invariant.
