A low power 10-bit 125-MSPS charge-domain(CD) pipelined analog-to-digital converter(ADC) based on MOS bucket-brigade devices(BBDs) is presented.A PVT insensitive boosted charge transfer(BCT) that is able to reject the...A low power 10-bit 125-MSPS charge-domain(CD) pipelined analog-to-digital converter(ADC) based on MOS bucket-brigade devices(BBDs) is presented.A PVT insensitive boosted charge transfer(BCT) that is able to reject the charge error induced by PVT variations is proposed.With the proposed BCT,the common mode charge control circuit can be eliminated in the CD pipelined ADC and the system complexity is reduced remarkably.The prototype ADC based on the proposed BCT is realized in a 0.18μm CMOS process,with power consumption of only 27 mW at 1.8-V supply and active die area of 1.04 mm^2.The prototype ADC achieves a spurious free dynamic range(SFDR) of 67.7 dB,a signal-to-noise ratio(SNDR) of 57.3 dB,and an effective number of bits(ENOB) of 9.0 for a 3.79 MHz input at full sampling rate.The measured differential nonlinearity(DNL) and integral nonlinearity (INL) are +0.5/-0.3 LSB and +0.7/-0.55 LSB,respectively.展开更多
A low power 10-bit 250 MSPS charge-domain （CD） pipelined analog-to-digital converter （ADC） is introduced. The ADC is implemented in MOS bucket-brigade devices （BBDs） based CD pipelined architecture. A replica co...A low power 10-bit 250 MSPS charge-domain （CD） pipelined analog-to-digital converter （ADC） is introduced. The ADC is implemented in MOS bucket-brigade devices （BBDs） based CD pipelined architecture. A replica controlled boosted charge transfer （BCT） circuit is introduced to reject the influence of PVT variations on the charge transfer process. Based on replica controlled BCT, the CD pipelined ADC is designed and realized in a 1P6M 0.18μm CMOS process. The ADC achieves an SFDR of 64.4 dB, an SNDR of 56.9 dB and an ENOB of 9.2 for a 9.9 MHz input; and an SFDR of 63.1 dB, an SNR of 55.2 dB, an SNDR of 54.5 dB and an ENOB of 8.7 for a 220.5 MHz input at full sampling rate. The DNL is ＋0.5/- 0.55 LSB and INL is ＋0.8/- 0.85 LSB. The power consumption of the prototype ADC is only 45 mW at 1.8 V supply and it occupies an active die area of 1.56 mm2.展开更多
提出了一种用于高速电荷域流水线模数转换器(Analog-to-Digital Converter,ADC)中的高精度大摆幅电荷传输电路,采用栅压自举技术,克服了现有电荷传输电路中信号摆幅受限的问题。基于该技术,采用0.18μm CMOS工艺,设计并实现了一款14位20...提出了一种用于高速电荷域流水线模数转换器(Analog-to-Digital Converter,ADC)中的高精度大摆幅电荷传输电路,采用栅压自举技术,克服了现有电荷传输电路中信号摆幅受限的问题。基于该技术,采用0.18μm CMOS工艺,设计并实现了一款14位200 MS/s电荷域流水线ADC。在189.9 MHz信号输入和全采样率条件下,信噪比为61.7 d BFS,无杂散动态范围为72.6 d Bc;在1.8 V供电下,ADC整体功耗仅为102 m W。展开更多
基金supported by the National Natural Science Foundation of China(No.61106027)the 333 Talent Project of Jiangsu Province, China(No.BRA2011115)
文摘A low power 10-bit 125-MSPS charge-domain(CD) pipelined analog-to-digital converter(ADC) based on MOS bucket-brigade devices(BBDs) is presented.A PVT insensitive boosted charge transfer(BCT) that is able to reject the charge error induced by PVT variations is proposed.With the proposed BCT,the common mode charge control circuit can be eliminated in the CD pipelined ADC and the system complexity is reduced remarkably.The prototype ADC based on the proposed BCT is realized in a 0.18μm CMOS process,with power consumption of only 27 mW at 1.8-V supply and active die area of 1.04 mm^2.The prototype ADC achieves a spurious free dynamic range(SFDR) of 67.7 dB,a signal-to-noise ratio(SNDR) of 57.3 dB,and an effective number of bits(ENOB) of 9.0 for a 3.79 MHz input at full sampling rate.The measured differential nonlinearity(DNL) and integral nonlinearity (INL) are +0.5/-0.3 LSB and +0.7/-0.55 LSB,respectively.
基金Project supported by the National Natural Science Foundation of China(No.61106027)
文摘A low power 10-bit 250 MSPS charge-domain （CD） pipelined analog-to-digital converter （ADC） is introduced. The ADC is implemented in MOS bucket-brigade devices （BBDs） based CD pipelined architecture. A replica controlled boosted charge transfer （BCT） circuit is introduced to reject the influence of PVT variations on the charge transfer process. Based on replica controlled BCT, the CD pipelined ADC is designed and realized in a 1P6M 0.18μm CMOS process. The ADC achieves an SFDR of 64.4 dB, an SNDR of 56.9 dB and an ENOB of 9.2 for a 9.9 MHz input; and an SFDR of 63.1 dB, an SNR of 55.2 dB, an SNDR of 54.5 dB and an ENOB of 8.7 for a 220.5 MHz input at full sampling rate. The DNL is ＋0.5/- 0.55 LSB and INL is ＋0.8/- 0.85 LSB. The power consumption of the prototype ADC is only 45 mW at 1.8 V supply and it occupies an active die area of 1.56 mm2.
文摘提出了一种用于高速电荷域流水线模数转换器(Analog-to-Digital Converter,ADC)中的高精度大摆幅电荷传输电路,采用栅压自举技术,克服了现有电荷传输电路中信号摆幅受限的问题。基于该技术,采用0.18μm CMOS工艺,设计并实现了一款14位200 MS/s电荷域流水线ADC。在189.9 MHz信号输入和全采样率条件下,信噪比为61.7 d BFS,无杂散动态范围为72.6 d Bc;在1.8 V供电下,ADC整体功耗仅为102 m W。
