A novel structure is proposed for doubling the vertical breakdown voltage of silicon-on-insulator（SOI） devices. In this new structure, the conventional buried oxide（BOX） in an SOI device is split into two sections...A novel structure is proposed for doubling the vertical breakdown voltage of silicon-on-insulator（SOI） devices. In this new structure, the conventional buried oxide（BOX） in an SOI device is split into two sections： the source-section BOX and the drain-section BOX. A highly-doped Si layer, referred to as a non-depletion potential-clamped layer（NPCL）, is positioned under and close to the two BOX sections. In the split BOXes and the Si region above the BOXes, the blocking voltage（BV） is divided into two parts by the NPCL. The voltage in the NPCL is clamped to be nearly half of the drain voltage. When the drain voltage approaches a breakdown value, the voltage sustained by the source-section BOX and the Si region under the source are nearly the same as the voltage sustained by the drain-section BOX and the Si region under the drain. The vertical BV is therefore almost doubled. The effectiveness of this new structure was verified for a P-channel SOI lateral double-diffused metal-oxide semiconductor（LDMOS） and can be applied to other high-voltage SOI devices. The simulation results show that the BV in an NPCL P-channel SOI LDMOS is improved by 55% and the specific on-resistance（Ron,sp） is reduced by 69% in comparison to the conventional structure.展开更多
A novel low specific on-resistance （Ron,sp） lateral double-diffused metal oxide semiconductor （LDMOS） with a buried improved super-junction （BISJ） layer is proposed. A super-junction layer is buried in the drift...A novel low specific on-resistance （Ron,sp） lateral double-diffused metal oxide semiconductor （LDMOS） with a buried improved super-junction （BISJ） layer is proposed. A super-junction layer is buried in the drift region and the P pillar is split into two parts with different doping concentrations. Firstly, the buried super-junction layer causes the multiple-direction assisted depletion effect. The drift region doping concentration of the BISJ LDMOS is therefore much higher than that of the conventional LDMOS. Secondly, the buried super-junction layer provides a bulk low on-resistance path. Both of them reduce Ron,sp greatly. Thirdly, the electric field modulation effect of the new electric field peak introduced by the step doped P pillar improves the breakdown voltage （BV）. The BISJ LDMOS exhibits a BV of 300 V and Ron,sp of 8.08 mΩ·cm2 which increases BV by 35% and reduces Ron,sp by 60% compared with those of a conventional LDMOS with a drift length of 15 μm, respectively.展开更多
In this manuscript we analyze a unique approach to improve the performance of the bipolar charge plasma transistor(BCPT) by introducing a strained Si/SiGe1-x layer as the active device region. For charge plasma realiz...In this manuscript we analyze a unique approach to improve the performance of the bipolar charge plasma transistor(BCPT) by introducing a strained Si/SiGe1-x layer as the active device region. For charge plasma realization different metal work-function electrodes are used to induce n+ and p+ regions on undoped strained silicon-on-insulator(sSOI or SiGe) to realize emitter, base, and collector regions of the BCPT. Here,by using a calibrated 2-D TCAD simulation the impact of a Si mole fraction x(in SiGe) on device performance metrics is investigated. The analysis demonstrates the band gap lowering with decreasing Si content or effective strain on the Si layer, and its subsequent advantages. This work reports a significant improvement in current gain, cutoff frequency, and lower collector breakdown voltage(BVCEO) for the proposed structure over the conventional device. The effect of varying temperature on the strained Si layer and its implications on the device performance is also investigated. The analysis demonstrates a fair device-level understanding and exhibits the immense potential of the SiGematerial as the device layer. In addition to this, using extensive 2-D mixed-mode TCAD simulation, a considerable improvement in switching transient times are also observed compared to its conventional counterpart.展开更多
基金supported by the National Natural Science Foundation of China(Grant No.61404110)the National Higher-Education Institution General Research and Development Project,China(Grant No.2682014CX097)
文摘A novel structure is proposed for doubling the vertical breakdown voltage of silicon-on-insulator（SOI） devices. In this new structure, the conventional buried oxide（BOX） in an SOI device is split into two sections： the source-section BOX and the drain-section BOX. A highly-doped Si layer, referred to as a non-depletion potential-clamped layer（NPCL）, is positioned under and close to the two BOX sections. In the split BOXes and the Si region above the BOXes, the blocking voltage（BV） is divided into two parts by the NPCL. The voltage in the NPCL is clamped to be nearly half of the drain voltage. When the drain voltage approaches a breakdown value, the voltage sustained by the source-section BOX and the Si region under the source are nearly the same as the voltage sustained by the drain-section BOX and the Si region under the drain. The vertical BV is therefore almost doubled. The effectiveness of this new structure was verified for a P-channel SOI lateral double-diffused metal-oxide semiconductor（LDMOS） and can be applied to other high-voltage SOI devices. The simulation results show that the BV in an NPCL P-channel SOI LDMOS is improved by 55% and the specific on-resistance（Ron,sp） is reduced by 69% in comparison to the conventional structure.
基金Project supported by the National Science and Technology Project of the Ministry of Science and Technology of China(Grant No.2010ZX02201)the National Natural Science Foundation of China(Grant No.61176069)the National Defense Pre-Research of China(Grant No.51308020304)
文摘A novel low specific on-resistance （Ron,sp） lateral double-diffused metal oxide semiconductor （LDMOS） with a buried improved super-junction （BISJ） layer is proposed. A super-junction layer is buried in the drift region and the P pillar is split into two parts with different doping concentrations. Firstly, the buried super-junction layer causes the multiple-direction assisted depletion effect. The drift region doping concentration of the BISJ LDMOS is therefore much higher than that of the conventional LDMOS. Secondly, the buried super-junction layer provides a bulk low on-resistance path. Both of them reduce Ron,sp greatly. Thirdly, the electric field modulation effect of the new electric field peak introduced by the step doped P pillar improves the breakdown voltage （BV）. The BISJ LDMOS exhibits a BV of 300 V and Ron,sp of 8.08 mΩ·cm2 which increases BV by 35% and reduces Ron,sp by 60% compared with those of a conventional LDMOS with a drift length of 15 μm, respectively.
文摘In this manuscript we analyze a unique approach to improve the performance of the bipolar charge plasma transistor(BCPT) by introducing a strained Si/SiGe1-x layer as the active device region. For charge plasma realization different metal work-function electrodes are used to induce n+ and p+ regions on undoped strained silicon-on-insulator(sSOI or SiGe) to realize emitter, base, and collector regions of the BCPT. Here,by using a calibrated 2-D TCAD simulation the impact of a Si mole fraction x(in SiGe) on device performance metrics is investigated. The analysis demonstrates the band gap lowering with decreasing Si content or effective strain on the Si layer, and its subsequent advantages. This work reports a significant improvement in current gain, cutoff frequency, and lower collector breakdown voltage(BVCEO) for the proposed structure over the conventional device. The effect of varying temperature on the strained Si layer and its implications on the device performance is also investigated. The analysis demonstrates a fair device-level understanding and exhibits the immense potential of the SiGematerial as the device layer. In addition to this, using extensive 2-D mixed-mode TCAD simulation, a considerable improvement in switching transient times are also observed compared to its conventional counterpart.
