We propose a reliable asymmetric dual-k spacer with SiC source/drain（S/D）pocket as a stressor for a Si channel.This enhances the device performance in terms of electron mobility（eMobility）,current driving capabili...We propose a reliable asymmetric dual-k spacer with SiC source/drain（S/D）pocket as a stressor for a Si channel.This enhances the device performance in terms of electron mobility（eMobility）,current driving capabilities,transconductance（G_m）and subthreshold slope（SS）.The improved performance is an amalgamation of longitudinal tensile stress along the channel and reduced series resistance.We analysed the variation in drive current for different values of carbon（C）mole fraction y in Si_（1-y）C_y.It is found that the mole fraction also helps to improve device lifetime,performance enhancement also pointed by transconductance variation with the gate length.All the simulations are performed in the 3-D Sentaurus TCAD tool.The proposed device structure achieved ION=2.17 mA/μm for Si_（0.3）C_（0.7） and found that Si_（0.5）C_（0.5） is more suitable for the perspective of a process variation effect for 14 nm as the gate length.We introduce reliability issues and their solutions for Si（1-y）Cy FinFET for the first time.展开更多
基金the M.P.Council of Science & Technology,Bhopal,India,for financial support under the R&D project scheme No:1950/CST/R&D/Phy & Engg Sc/2015:27~(th) Aug 2015
文摘We propose a reliable asymmetric dual-k spacer with SiC source/drain（S/D）pocket as a stressor for a Si channel.This enhances the device performance in terms of electron mobility（eMobility）,current driving capabilities,transconductance（G_m）and subthreshold slope（SS）.The improved performance is an amalgamation of longitudinal tensile stress along the channel and reduced series resistance.We analysed the variation in drive current for different values of carbon（C）mole fraction y in Si_（1-y）C_y.It is found that the mole fraction also helps to improve device lifetime,performance enhancement also pointed by transconductance variation with the gate length.All the simulations are performed in the 3-D Sentaurus TCAD tool.The proposed device structure achieved ION=2.17 mA/μm for Si_（0.3）C_（0.7） and found that Si_（0.5）C_（0.5） is more suitable for the perspective of a process variation effect for 14 nm as the gate length.We introduce reliability issues and their solutions for Si（1-y）Cy FinFET for the first time.
