Two of the main challenges in optimal control are solving problems with state-dependent running costs and developing efficient numerical solvers that are computationally tractable in high dimensions.In this paper,we p...Two of the main challenges in optimal control are solving problems with state-dependent running costs and developing efficient numerical solvers that are computationally tractable in high dimensions.In this paper,we provide analytical solutions to certain optimal control problems whose running cost depends on the state variable and with constraints on the control.We also provide Lax-Oleinik-type representation formulas for the corresponding Hamilton-Jacobi partial differential equations with state-dependent Hamiltonians.Additionally,we present an efficient,grid-free numerical solver based on our representation formulas,which is shown to scale linearly with the state dimension,and thus,to overcome the curse of dimensionality.Using existing optimization methods and the min-plus technique,we extend our numerical solvers to address more general classes of convex and nonconvex initial costs.We demonstrate the capabilities of our numerical solvers using implementations on a central processing unit(CPU)and a field-programmable gate array(FPGA).In several cases,our FPGA implementation obtains over a 10 times speedup compared to the CPU,which demonstrates the promising performance boosts FPGAs can achieve.Our numerical results show that our solvers have the potential to serve as a building block for solving broader classes of high-dimensional optimal control problems in real-time.展开更多
This paper addresses the issue of designing the detailed architectures of Field-Programmable Gate Arrays(FPGAs), which has a great impact on the overall performances of an FPGA in practice. Firstly, a novel FPGA archi...This paper addresses the issue of designing the detailed architectures of Field-Programmable Gate Arrays(FPGAs), which has a great impact on the overall performances of an FPGA in practice. Firstly, a novel FPGA architecture description model is proposed based on an easy-to-use file format known as YAML. This format permits the description of any detailed architecture of hard blocks and channels. Then a general algorithm of building FPGA resource graph is presented. The proposed model is scalable and capable of dealing with detailed architecture design and can be used in FPGA architecture evaluation system which is developed to enable detailed architecture design. Experimental results show that a maximum of 16.36% reduction in total wirelength and a maximum of 9.34% reduction in router effort can be obtained by making very little changes to detailed architectures, which verifies the necessity and effectiveness of the proposed model.展开更多
Field Programmable Gate Arrays(FPGAs)offer high capability in implementing of complex systems,and currently are an attractive solution for space system electronics.However,FPGAs are susceptible to radiation induced Si...Field Programmable Gate Arrays(FPGAs)offer high capability in implementing of complex systems,and currently are an attractive solution for space system electronics.However,FPGAs are susceptible to radiation induced Single-Event Upsets(SEUs).To insure reliable operation of FPGA based systems in a harsh radiation environment,various SEU mitigation techniques have been provided.In this paper we propose a system based on dynamic partial reconfiguration capability of the modern devices to evaluate the SEU fault effect in FPGA.The proposed approach combines the fault injection controller with the host FPGA,and therefore the hardware complexity is minimized.All of the SEU injection and evaluation requirements are performed by a soft-core which realized inside the host FPGA.Experimental results on some standard benchmark circuits reveal that the proposed system is able to speed up the fault injection campaign 50 times in compared to conventional method.展开更多
基金supported by the DOE-MMICS SEA-CROGS DE-SC0023191 and the AFOSR MURI FA9550-20-1-0358supported by the SMART Scholarship,which is funded by the USD/R&E(The Under Secretary of Defense-Research and Engineering),National Defense Education Program(NDEP)/BA-1,Basic Research.
文摘Two of the main challenges in optimal control are solving problems with state-dependent running costs and developing efficient numerical solvers that are computationally tractable in high dimensions.In this paper,we provide analytical solutions to certain optimal control problems whose running cost depends on the state variable and with constraints on the control.We also provide Lax-Oleinik-type representation formulas for the corresponding Hamilton-Jacobi partial differential equations with state-dependent Hamiltonians.Additionally,we present an efficient,grid-free numerical solver based on our representation formulas,which is shown to scale linearly with the state dimension,and thus,to overcome the curse of dimensionality.Using existing optimization methods and the min-plus technique,we extend our numerical solvers to address more general classes of convex and nonconvex initial costs.We demonstrate the capabilities of our numerical solvers using implementations on a central processing unit(CPU)and a field-programmable gate array(FPGA).In several cases,our FPGA implementation obtains over a 10 times speedup compared to the CPU,which demonstrates the promising performance boosts FPGAs can achieve.Our numerical results show that our solvers have the potential to serve as a building block for solving broader classes of high-dimensional optimal control problems in real-time.
基金Supported by National High Technology Research and Develop Program of China(No.2012AA012301)National Science and Technology Major Project of China(No.2013ZX03006004)
文摘This paper addresses the issue of designing the detailed architectures of Field-Programmable Gate Arrays(FPGAs), which has a great impact on the overall performances of an FPGA in practice. Firstly, a novel FPGA architecture description model is proposed based on an easy-to-use file format known as YAML. This format permits the description of any detailed architecture of hard blocks and channels. Then a general algorithm of building FPGA resource graph is presented. The proposed model is scalable and capable of dealing with detailed architecture design and can be used in FPGA architecture evaluation system which is developed to enable detailed architecture design. Experimental results show that a maximum of 16.36% reduction in total wirelength and a maximum of 9.34% reduction in router effort can be obtained by making very little changes to detailed architectures, which verifies the necessity and effectiveness of the proposed model.
文摘Field Programmable Gate Arrays(FPGAs)offer high capability in implementing of complex systems,and currently are an attractive solution for space system electronics.However,FPGAs are susceptible to radiation induced Single-Event Upsets(SEUs).To insure reliable operation of FPGA based systems in a harsh radiation environment,various SEU mitigation techniques have been provided.In this paper we propose a system based on dynamic partial reconfiguration capability of the modern devices to evaluate the SEU fault effect in FPGA.The proposed approach combines the fault injection controller with the host FPGA,and therefore the hardware complexity is minimized.All of the SEU injection and evaluation requirements are performed by a soft-core which realized inside the host FPGA.Experimental results on some standard benchmark circuits reveal that the proposed system is able to speed up the fault injection campaign 50 times in compared to conventional method.
