Soft errors have become a critical challenge as a result of technology scaling. Existing circuit-hardening techniques are commonly associated with prohibitive overhead of performance, area, and power. However,evaluati...Soft errors have become a critical challenge as a result of technology scaling. Existing circuit-hardening techniques are commonly associated with prohibitive overhead of performance, area, and power. However,evaluating the influence of soft errors in Flip-Flops(FFs) on the failure of circuit is a difficult verification problem.Here, we proposed a novel flip-flop soft-error failure rate analysis methodology using a formal method with respect to application behaviors. Approach and optimization techniques to implement the proposed methodology based on the given formula using Sequential Equivalence Checking(SEC) are introduced. The proposed method combines the advantage of formal technique-based approaches in completeness and the advantage of application behaviors in accuracy to differentiate vulnerability of components. As a result, the FFs in a circuit are sorted by their failure rates, and designers can use this information to perform optimal hardening of selected sequential components against soft errors. Experimental results of an implementation of a SpaceWire end node and the largest ISCAS’89 benchmark sequential circuits indicate the feasibility and potential scalability of our approach. A case study on an instruction decoder of a practical 32-bit microprocessor demonstrates the applicability of our method.展开更多
Modern pixel detectors in nuclear and particle physics experiments and also in nuclear imaging,starve for highly integrated application specified integrated circuit(ASIC),whereas in China the study of ASIC still stays...Modern pixel detectors in nuclear and particle physics experiments and also in nuclear imaging,starve for highly integrated application specified integrated circuit(ASIC),whereas in China the study of ASIC still stays far away from practical application.The lack of ASIC strictly limits the research and development of domestic high energy physics field.A 12-bit multichannel ADC designed for high density readout is introduced as a major candidate for solution.A precise model is discussed and the simulation fully agrees with the model,which indicates a key principle of design.Design is performed according to the given rule,and novel layout techniques are carried out.Measurement results in all aspects are also obtained,showing an excellent real performance,which satisfies the practical requirement.展开更多
基金supported by the National Key Basic R&D Program (973) of China (No. 2017YFB1001802)
文摘Soft errors have become a critical challenge as a result of technology scaling. Existing circuit-hardening techniques are commonly associated with prohibitive overhead of performance, area, and power. However,evaluating the influence of soft errors in Flip-Flops(FFs) on the failure of circuit is a difficult verification problem.Here, we proposed a novel flip-flop soft-error failure rate analysis methodology using a formal method with respect to application behaviors. Approach and optimization techniques to implement the proposed methodology based on the given formula using Sequential Equivalence Checking(SEC) are introduced. The proposed method combines the advantage of formal technique-based approaches in completeness and the advantage of application behaviors in accuracy to differentiate vulnerability of components. As a result, the FFs in a circuit are sorted by their failure rates, and designers can use this information to perform optimal hardening of selected sequential components against soft errors. Experimental results of an implementation of a SpaceWire end node and the largest ISCAS’89 benchmark sequential circuits indicate the feasibility and potential scalability of our approach. A case study on an instruction decoder of a practical 32-bit microprocessor demonstrates the applicability of our method.
基金supported by the National Natural Science Foundation of China (Grant No.10735060)
文摘Modern pixel detectors in nuclear and particle physics experiments and also in nuclear imaging,starve for highly integrated application specified integrated circuit(ASIC),whereas in China the study of ASIC still stays far away from practical application.The lack of ASIC strictly limits the research and development of domestic high energy physics field.A 12-bit multichannel ADC designed for high density readout is introduced as a major candidate for solution.A precise model is discussed and the simulation fully agrees with the model,which indicates a key principle of design.Design is performed according to the given rule,and novel layout techniques are carried out.Measurement results in all aspects are also obtained,showing an excellent real performance,which satisfies the practical requirement.
