基于跟踪法的磁编码器轴角转换单元具有抗干扰能力强,同时能得到角度和速度信号等优点;而专用集成电路具有并行性、灵活性和实时性高等优点。当采用专用集成电路(application specific integrated circuits,ASIC)设计全数字、纯硬件的...基于跟踪法的磁编码器轴角转换单元具有抗干扰能力强,同时能得到角度和速度信号等优点;而专用集成电路具有并行性、灵活性和实时性高等优点。当采用专用集成电路(application specific integrated circuits,ASIC)设计全数字、纯硬件的轴角数字转换单元时,面临着系统和算法的结构选择、内部参数界确定以及字长选取等问题。该文利用数字坐标旋转机(coordinate rotational digital computer,CORDIC)算法来替代传统跟踪测角中的乘法器和数控振荡器,通过对XY通道和Z通道进行标定以及误差分析,将其等效为一个减法操作符,实现角度求差功能。在此基础上,分析内部的误差传播路径,并从稳定性和动态性能角度确定传播路径的界,从而建立全数字轴角转换单元的模型,最后利用FPGA分别实现了A/D位数为10位、12位和14位时的轴角转换单元。实验结果验证了该文所建模型的正确性及有效性。展开更多
随着工业技术的进步,高温高动态压力传感器的应用需求显著增加。提出一种集成专用补偿电路的高动态硅压阻式微电子机械系统(Micro-Electro-Mechanical Systems,MEMS)压力传感器,进行压力敏感芯片的结构设计和加工工艺设计,并对压力传感...随着工业技术的进步,高温高动态压力传感器的应用需求显著增加。提出一种集成专用补偿电路的高动态硅压阻式微电子机械系统(Micro-Electro-Mechanical Systems,MEMS)压力传感器,进行压力敏感芯片的结构设计和加工工艺设计,并对压力传感器进行封装和温度补偿电路设计。多层绝缘体上硅(Silicon On Insulator,SOI)材料能够使传感器在高温环境下正常工作。无引线的封装方式可有效提升传感器的频响性能。传感器后端集成了桥阻式专用集成电路(Application Specific Integrated Circuits,ASIC),能够显著减小传感器的体积,同时提升传感器整体性能。该MEMS传感器通过自动压力测试系统进行性能试验,结果表明MEMS压力传感器经过补偿后能够实现较高的线性度、稳定的零点输出特性以及理想的动态输出特性。展开更多
A low-power and low-cost advanced encryption standard （AES） coprocessor is proposed for Zigbee system-on-a-chip （SoC） design. The cost and power consumption of the proposed AES coprocessor are reduced considerably...A low-power and low-cost advanced encryption standard （AES） coprocessor is proposed for Zigbee system-on-a-chip （SoC） design. The cost and power consumption of the proposed AES coprocessor are reduced considerably by optimizing the architectures of SubBytes/InvSubBytes and MixColumns/InvMixColumns, integrating the encryption and decryption procedures together by the method of resource sharing, and using the hierarchical power management strategy based on finite state machine （FSM） and clock gating （CG） technologies. Based on SMIC 0.18 μm complementary metal oxide semiconductor （CMOS） technology, the scale of the AES coprocessor is only about 10.5 kgate, the corresponding power consumption is 69.1 μW/MHz, and the throughput is 32 Mb/s, which is reasonable and sufficient for Zigbee system. Compared with other designs, the proposed architecture consumes less power and fewer hardware resources, which is conducive to the Zigbee system and other portable devices.展开更多
An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields...An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields. Several novel design techniques for floating-point adder and multiplier are introduced in detail to enhance the speed of the system. At the same time, the power consumption is decreased. The hardware area is effectively reduced as an improved butterfly processor is developed. There is a substantial increase in the performance of the design since a pipelined architecture is adopted, and very large scale integrated (VLSI) is easy to realize due to the regularity. A result of validation using field programmable gate array (FPGA) is shown at the end. When the system clock is set to 50 MHz, 204.8 μs is needed to complete the operation of FFT computation.展开更多
为解决里所(Reed-solomon,RS)编码的低功耗设计,从系统架构、RTL级、门级等不同设计层级进行分析,并在专用集成电路(Application specific integrated circuit,ASIC)设计中加以实践。基于低功耗设计将前端RTL级设计与后端IC设计结合起来...为解决里所(Reed-solomon,RS)编码的低功耗设计,从系统架构、RTL级、门级等不同设计层级进行分析,并在专用集成电路(Application specific integrated circuit,ASIC)设计中加以实践。基于低功耗设计将前端RTL级设计与后端IC设计结合起来,研究能实现RS编码功能的芯片。在系统架构层,针对RS编码算法中伽罗华域的乘法运算在硬件实现时存在数据运算量大、消耗功耗大等问题,提出基于乘法器因子矩阵的方法对RS编码算法进行优化,通过将乘法运算转化为减法运算等方式减少数据运算量,从而降低功耗。在RTL级和门级层面,分别在逻辑综合和后端实现中加以约束来实现低功耗设计,总体功耗可以降低60%左右。解决了因IC芯片功耗过高导致芯片性能下降,从而影响芯片正常工作等问题,为集成电路工艺提供了新的发展方向。展开更多
为了提高水轮机调速器的可靠性,对全数字式水轮机调速器进行了研究,它以可编程控制器(PLC)为基础,结合专用集成电路技术(application specific integrated circuit,ASIC)进行测频和位移测量,同时采用一个全数字式的液压控制系统——数...为了提高水轮机调速器的可靠性,对全数字式水轮机调速器进行了研究,它以可编程控制器(PLC)为基础,结合专用集成电路技术(application specific integrated circuit,ASIC)进行测频和位移测量,同时采用一个全数字式的液压控制系统——数字阀插装阀并联液压控制系统,从而构成一个真正的全数字式水轮机调速器,即从信号的采集到控制的输出全部实现了数字化.在水轮机调速器半物理仿真实验台上进行了实验.结果表明,它的控制性能良好,可以满足水轮机对调速器的要求.展开更多
文摘基于跟踪法的磁编码器轴角转换单元具有抗干扰能力强,同时能得到角度和速度信号等优点;而专用集成电路具有并行性、灵活性和实时性高等优点。当采用专用集成电路(application specific integrated circuits,ASIC)设计全数字、纯硬件的轴角数字转换单元时,面临着系统和算法的结构选择、内部参数界确定以及字长选取等问题。该文利用数字坐标旋转机(coordinate rotational digital computer,CORDIC)算法来替代传统跟踪测角中的乘法器和数控振荡器,通过对XY通道和Z通道进行标定以及误差分析,将其等效为一个减法操作符,实现角度求差功能。在此基础上,分析内部的误差传播路径,并从稳定性和动态性能角度确定传播路径的界,从而建立全数字轴角转换单元的模型,最后利用FPGA分别实现了A/D位数为10位、12位和14位时的轴角转换单元。实验结果验证了该文所建模型的正确性及有效性。
文摘随着工业技术的进步,高温高动态压力传感器的应用需求显著增加。提出一种集成专用补偿电路的高动态硅压阻式微电子机械系统(Micro-Electro-Mechanical Systems,MEMS)压力传感器,进行压力敏感芯片的结构设计和加工工艺设计,并对压力传感器进行封装和温度补偿电路设计。多层绝缘体上硅(Silicon On Insulator,SOI)材料能够使传感器在高温环境下正常工作。无引线的封装方式可有效提升传感器的频响性能。传感器后端集成了桥阻式专用集成电路(Application Specific Integrated Circuits,ASIC),能够显著减小传感器的体积,同时提升传感器整体性能。该MEMS传感器通过自动压力测试系统进行性能试验,结果表明MEMS压力传感器经过补偿后能够实现较高的线性度、稳定的零点输出特性以及理想的动态输出特性。
基金supported by the National Natural Science Foundation of China(60676053)
文摘A low-power and low-cost advanced encryption standard （AES） coprocessor is proposed for Zigbee system-on-a-chip （SoC） design. The cost and power consumption of the proposed AES coprocessor are reduced considerably by optimizing the architectures of SubBytes/InvSubBytes and MixColumns/InvMixColumns, integrating the encryption and decryption procedures together by the method of resource sharing, and using the hierarchical power management strategy based on finite state machine （FSM） and clock gating （CG） technologies. Based on SMIC 0.18 μm complementary metal oxide semiconductor （CMOS） technology, the scale of the AES coprocessor is only about 10.5 kgate, the corresponding power consumption is 69.1 μW/MHz, and the throughput is 32 Mb/s, which is reasonable and sufficient for Zigbee system. Compared with other designs, the proposed architecture consumes less power and fewer hardware resources, which is conducive to the Zigbee system and other portable devices.
文摘An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields. Several novel design techniques for floating-point adder and multiplier are introduced in detail to enhance the speed of the system. At the same time, the power consumption is decreased. The hardware area is effectively reduced as an improved butterfly processor is developed. There is a substantial increase in the performance of the design since a pipelined architecture is adopted, and very large scale integrated (VLSI) is easy to realize due to the regularity. A result of validation using field programmable gate array (FPGA) is shown at the end. When the system clock is set to 50 MHz, 204.8 μs is needed to complete the operation of FFT computation.
文摘为解决里所(Reed-solomon,RS)编码的低功耗设计,从系统架构、RTL级、门级等不同设计层级进行分析,并在专用集成电路(Application specific integrated circuit,ASIC)设计中加以实践。基于低功耗设计将前端RTL级设计与后端IC设计结合起来,研究能实现RS编码功能的芯片。在系统架构层,针对RS编码算法中伽罗华域的乘法运算在硬件实现时存在数据运算量大、消耗功耗大等问题,提出基于乘法器因子矩阵的方法对RS编码算法进行优化,通过将乘法运算转化为减法运算等方式减少数据运算量,从而降低功耗。在RTL级和门级层面,分别在逻辑综合和后端实现中加以约束来实现低功耗设计,总体功耗可以降低60%左右。解决了因IC芯片功耗过高导致芯片性能下降,从而影响芯片正常工作等问题,为集成电路工艺提供了新的发展方向。
文摘为了提高水轮机调速器的可靠性,对全数字式水轮机调速器进行了研究,它以可编程控制器(PLC)为基础,结合专用集成电路技术(application specific integrated circuit,ASIC)进行测频和位移测量,同时采用一个全数字式的液压控制系统——数字阀插装阀并联液压控制系统,从而构成一个真正的全数字式水轮机调速器,即从信号的采集到控制的输出全部实现了数字化.在水轮机调速器半物理仿真实验台上进行了实验.结果表明,它的控制性能良好,可以满足水轮机对调速器的要求.
