A low-power and low-cost advanced encryption standard （AES） coprocessor is proposed for Zigbee system-on-a-chip （SoC） design. The cost and power consumption of the proposed AES coprocessor are reduced considerably...A low-power and low-cost advanced encryption standard （AES） coprocessor is proposed for Zigbee system-on-a-chip （SoC） design. The cost and power consumption of the proposed AES coprocessor are reduced considerably by optimizing the architectures of SubBytes/InvSubBytes and MixColumns/InvMixColumns, integrating the encryption and decryption procedures together by the method of resource sharing, and using the hierarchical power management strategy based on finite state machine （FSM） and clock gating （CG） technologies. Based on SMIC 0.18 μm complementary metal oxide semiconductor （CMOS） technology, the scale of the AES coprocessor is only about 10.5 kgate, the corresponding power consumption is 69.1 μW/MHz, and the throughput is 32 Mb/s, which is reasonable and sufficient for Zigbee system. Compared with other designs, the proposed architecture consumes less power and fewer hardware resources, which is conducive to the Zigbee system and other portable devices.展开更多
An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields...An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields. Several novel design techniques for floating-point adder and multiplier are introduced in detail to enhance the speed of the system. At the same time, the power consumption is decreased. The hardware area is effectively reduced as an improved butterfly processor is developed. There is a substantial increase in the performance of the design since a pipelined architecture is adopted, and very large scale integrated (VLSI) is easy to realize due to the regularity. A result of validation using field programmable gate array (FPGA) is shown at the end. When the system clock is set to 50 MHz, 204.8 μs is needed to complete the operation of FFT computation.展开更多
为解决里所(Reed-solomon,RS)编码的低功耗设计,从系统架构、RTL级、门级等不同设计层级进行分析,并在专用集成电路(Application specific integrated circuit,ASIC)设计中加以实践。基于低功耗设计将前端RTL级设计与后端IC设计结合起来...为解决里所(Reed-solomon,RS)编码的低功耗设计,从系统架构、RTL级、门级等不同设计层级进行分析,并在专用集成电路(Application specific integrated circuit,ASIC)设计中加以实践。基于低功耗设计将前端RTL级设计与后端IC设计结合起来,研究能实现RS编码功能的芯片。在系统架构层,针对RS编码算法中伽罗华域的乘法运算在硬件实现时存在数据运算量大、消耗功耗大等问题,提出基于乘法器因子矩阵的方法对RS编码算法进行优化,通过将乘法运算转化为减法运算等方式减少数据运算量,从而降低功耗。在RTL级和门级层面,分别在逻辑综合和后端实现中加以约束来实现低功耗设计,总体功耗可以降低60%左右。解决了因IC芯片功耗过高导致芯片性能下降,从而影响芯片正常工作等问题,为集成电路工艺提供了新的发展方向。展开更多
为了提高水轮机调速器的可靠性,对全数字式水轮机调速器进行了研究,它以可编程控制器(PLC)为基础,结合专用集成电路技术(application specific integrated circuit,ASIC)进行测频和位移测量,同时采用一个全数字式的液压控制系统——数...为了提高水轮机调速器的可靠性,对全数字式水轮机调速器进行了研究,它以可编程控制器(PLC)为基础,结合专用集成电路技术(application specific integrated circuit,ASIC)进行测频和位移测量,同时采用一个全数字式的液压控制系统——数字阀插装阀并联液压控制系统,从而构成一个真正的全数字式水轮机调速器,即从信号的采集到控制的输出全部实现了数字化.在水轮机调速器半物理仿真实验台上进行了实验.结果表明,它的控制性能良好,可以满足水轮机对调速器的要求.展开更多
基金supported by the National Natural Science Foundation of China(60676053)
文摘A low-power and low-cost advanced encryption standard （AES） coprocessor is proposed for Zigbee system-on-a-chip （SoC） design. The cost and power consumption of the proposed AES coprocessor are reduced considerably by optimizing the architectures of SubBytes/InvSubBytes and MixColumns/InvMixColumns, integrating the encryption and decryption procedures together by the method of resource sharing, and using the hierarchical power management strategy based on finite state machine （FSM） and clock gating （CG） technologies. Based on SMIC 0.18 μm complementary metal oxide semiconductor （CMOS） technology, the scale of the AES coprocessor is only about 10.5 kgate, the corresponding power consumption is 69.1 μW/MHz, and the throughput is 32 Mb/s, which is reasonable and sufficient for Zigbee system. Compared with other designs, the proposed architecture consumes less power and fewer hardware resources, which is conducive to the Zigbee system and other portable devices.
文摘An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields. Several novel design techniques for floating-point adder and multiplier are introduced in detail to enhance the speed of the system. At the same time, the power consumption is decreased. The hardware area is effectively reduced as an improved butterfly processor is developed. There is a substantial increase in the performance of the design since a pipelined architecture is adopted, and very large scale integrated (VLSI) is easy to realize due to the regularity. A result of validation using field programmable gate array (FPGA) is shown at the end. When the system clock is set to 50 MHz, 204.8 μs is needed to complete the operation of FFT computation.
文摘为解决里所(Reed-solomon,RS)编码的低功耗设计,从系统架构、RTL级、门级等不同设计层级进行分析,并在专用集成电路(Application specific integrated circuit,ASIC)设计中加以实践。基于低功耗设计将前端RTL级设计与后端IC设计结合起来,研究能实现RS编码功能的芯片。在系统架构层,针对RS编码算法中伽罗华域的乘法运算在硬件实现时存在数据运算量大、消耗功耗大等问题,提出基于乘法器因子矩阵的方法对RS编码算法进行优化,通过将乘法运算转化为减法运算等方式减少数据运算量,从而降低功耗。在RTL级和门级层面,分别在逻辑综合和后端实现中加以约束来实现低功耗设计,总体功耗可以降低60%左右。解决了因IC芯片功耗过高导致芯片性能下降,从而影响芯片正常工作等问题,为集成电路工艺提供了新的发展方向。
文摘为了提高水轮机调速器的可靠性,对全数字式水轮机调速器进行了研究,它以可编程控制器(PLC)为基础,结合专用集成电路技术(application specific integrated circuit,ASIC)进行测频和位移测量,同时采用一个全数字式的液压控制系统——数字阀插装阀并联液压控制系统,从而构成一个真正的全数字式水轮机调速器,即从信号的采集到控制的输出全部实现了数字化.在水轮机调速器半物理仿真实验台上进行了实验.结果表明,它的控制性能良好,可以满足水轮机对调速器的要求.
