The electromagnetic radiation will result in informa- tion leakage being recovered when computers work. This article presents a high-speed real-time data acquisition system based on peripheral component interconnect ...The electromagnetic radiation will result in informa- tion leakage being recovered when computers work. This article presents a high-speed real-time data acquisition system based on peripheral component interconnect （PCI） bus and field programmable gate array （FPGA） for sampling electromagnetic radiation caused by video signal. The hardware design and controlling flow of each module are introduced in detail. The sampling rate can reach 64 Msps and system transfers speed can be up to 128 Mb/s by using time interleaving, which increases the overall sampling speed of a system by operating two data converters in parallel.展开更多
A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor shari...A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.展开更多
Addressing the impact of capacitor mismatch on the conversion accuracy of successive approximation register analog-to-digital converter(SAR ADC),a 12-bit 1 MS/s sub-binary SAR ADC designed using variable step size dig...Addressing the impact of capacitor mismatch on the conversion accuracy of successive approximation register analog-to-digital converter(SAR ADC),a 12-bit 1 MS/s sub-binary SAR ADC designed using variable step size digital calibration was proposed.The least mean square(LMS)calibration algorithm was employed with a ramp signal used as the calibration input.Weight errors,extracted under injected disturbances,underwent iterative training to optimize weight values.To address the trade-off between conversion accuracy and speed caused by a fixed step size,a novel variable step size algorithm tailored for SAR ADC calibration was proposed.The core circuit and layout of the SAR ADC were implemented using the Taiwan Semiconductor Manufacturing Company(TSMC)0.35μm complementary metal-oxide-semiconductor(CMOS)commercial process.Simulation of the SAR ADC calibration algorithm was conducted using Simulink,demonstrating quick convergence and meeting conversion accuracy requirements compared to fixed step size simulation.The results indicated that the convergence speed of the LMS digital calibration algorithm with variable step size was approximately eight times faster than that with a fixed step size,also yielding a lower mean square error(MSE).After calibration,the simulation results for the SAR ADC exhibited an effective number of bit(ENOB)of 11.79 bit and a signal-to-noise and distortion ratio(SNDR)of 72.72 dB,signifying a notable enhancement in the SAR ADC performance.展开更多
This paper presents a 12-bit column-parallel successive approximation register analog-to-digital con- verter （SAR ADC） for high-speed CMOS image sensors. A segmented binary-weighted switched capacitor digital- to-an...This paper presents a 12-bit column-parallel successive approximation register analog-to-digital con- verter （SAR ADC） for high-speed CMOS image sensors. A segmented binary-weighted switched capacitor digital- to-analog converter （CDAC） and a staggered structure MOM unit capacitor is used to reduce the ADC area and to make its layout fit double pixel pitches. An electrical field shielding layout method is proposed to eliminate the parasitic capacitance on the top plate of the unit capacitor. A dynamic power control technique is proposed to reduce the power consumption of a single channel during readout. An off-chip foreground digital calibration is adopted to compensate for the nonlinearity due to the mismatch of unit capacitors among the CDAC. The prototype SAR ADC is fabricated in a 0.18 μm 1P5M CIS process. A single SAR ADC occupies 20 × 2020μm2. Sampling at 833 kS/s, the measured differential nonlinearity, integral nonlinearity and effective number of bits of SAR ADC with calibration are 0.9/-1 LSB, 1/-1.1 LSB and 11.24 bits, respectively; the power consumption is only 0.26 mW under a 1.8-W supply and decreases linearly as the frame rate decreases.展开更多
This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters （ADC）. The new offset averaging design technique takes full advantage of t...This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters （ADC）. The new offset averaging design technique takes full advantage of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging techniques to minimize offset-induced ADC nonlinearities. Circuit analysis allows selection of optimum resistance and capacitance averaging factors to achieve maximum offset reduction in ADC designs. The new averaging method is verified in designing a 4 bit 1 Gs/s flash ADC that is implemented in foundry 0.13 μm CMOS technology.展开更多
A novel Time-Interleaved Analog-to-Digital Converter (TIADC) digital background calibration for the mismatches of offsets, gain errors, and timing skews based on split-ADC is proposed. Firstly, the split-ADC channels ...A novel Time-Interleaved Analog-to-Digital Converter (TIADC) digital background calibration for the mismatches of offsets, gain errors, and timing skews based on split-ADC is proposed. Firstly, the split-ADC channels in present TIADC architecture are designed to convert input signal at two different channel sampling rates so that redundant channel to facilitate pair permutation is avoided. Secondly, a high-order compensation scheme for correction of timing skew error is employed for effective calibration to preserve high-resolution when input frequency is high. Numerical simulation performed by MATLAB for a 14-bit TIADC based on 7 split-ADC channels shows that Signal-to-Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) of the TIADC achieve 86.2 dBc and 106 dBc respectively after calibration with normalized input frequency near Nyquist frequency.展开更多
With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to co...With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.展开更多
As deep learning techniques such as Convolutional Neural Networks(CNNs)are widely adopted,the complexity of CNNs is rapidly increasing due to the growing demand for CNN accelerator system-on-chip(SoC).Although convent...As deep learning techniques such as Convolutional Neural Networks(CNNs)are widely adopted,the complexity of CNNs is rapidly increasing due to the growing demand for CNN accelerator system-on-chip(SoC).Although conventional CNN accelerators can reduce the computational time of learning and inference tasks,they tend to occupy large chip areas due to many multiply-and-accumulate(MAC)operators when implemented in complex digital circuits,incurring excessive power consumption.To overcome these drawbacks,this work implements an analog convolutional filter consisting of an analog multiply-and-accumulate arithmetic circuit along with an analog-to-digital converter(ADC).This paper introduces the architecture of an analog convolutional kernel comprised of low-power ultra-small circuits for neural network accelerator chips.ADC is an essential component of the analog convolutional kernel used to convert the analog convolutional result to digital values to be stored in memory.This work presents the implementation of a highly low-power and area-efficient 12-bit Successive Approximation Register(SAR)ADC.Unlink most other SAR-ADCs with differential structure;the proposed ADC employs a single-ended capacitor array to support the preceding single-ended max-pooling circuit along with minimal power consumption.The SARADCimplementation also introduces a unique circuit that reduces kick-back noise to increase performance.It was implemented in a test chip using a 55 nm CMOS process.It demonstrates that the proposed ADC reduces Kick-back noise by 40%and consequently improves the ADC’s resolution by about 10%while providing a near rail-to-rail dynamic rangewith significantly lower power consumption than conventional ADCs.The ADC test chip shows a chip size of 4600μm^(2)with a power consumption of 6.6μW while providing an signal-to-noise-and-distortion ratio(SNDR)of 68.45 dB,corresponding to an effective number of bits(ENOB)of 11.07 bits.展开更多
A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital con- verter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3...A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital con- verter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.展开更多
This paper presents a low-power high-precision switched-opamp（SO）-based delta-sigma（△Σ） analog-to -digital converter（ADC）.The proposed SO design allows circuit operation at sub-1 V supply voltage,only needs to...This paper presents a low-power high-precision switched-opamp（SO）-based delta-sigma（△Σ） analog-to -digital converter（ADC）.The proposed SO design allows circuit operation at sub-1 V supply voltage,only needs to work in half of a clock cycle,and thus is suitable for low power applications.In addition,an opamp-sharing technique is applied to save on hardware overheads.Due to the use of a dual cycle shift data weighted averaging （DCS-DWA） technique,mismatch errors caused in the feedback DAC have been eliminated without introducing signal-dependent tones.The proposed ADC has been implemented in a standard 0.18μm process and measured to have a 92.2 dB peak SNDR and 94.1 dB dynamic range with 25 kHz signal bandwidth.The power consumption is 58μW for the modulator at 0.9 V supply voltage and 96μW for the decimation filter,which translate to the figure-of-merit（FOM） of 35.4 fJ/step for the solo modulator,and 94 fJ/step for the whole system.展开更多
This Letter theoretically and experimentally studies the response of photonic switching in a channel-interleaved photonic analog-to-digital converter(PADC) with high sampling rate and wide input frequency range. A fig...This Letter theoretically and experimentally studies the response of photonic switching in a channel-interleaved photonic analog-to-digital converter(PADC) with high sampling rate and wide input frequency range. A figure of merit(FoM) is introduced to evaluate the switching response of the PADC when a dual-output Mach–Zehnder modulator(MZM) serves as the photonic switch to parallelize the sampled pulse train into two channels. After the optimization of the FoM and utilization of the channel-mismatch compensation algorithm,the system bandwidth of PADC is expanded and the signal-to-distortion ratio is enhanced.展开更多
We investigate a channel-interleaved photonic analog-to-digital conversion(PADC)system’s ability to work stably over a long duration with an optimal driving voltage.The influence of optimum bias point drift of a Mach...We investigate a channel-interleaved photonic analog-to-digital conversion(PADC)system’s ability to work stably over a long duration with an optimal driving voltage.The influence of optimum bias point drift of a Mach–Zehnder modulator(MZM)-based photonic switch on this system was analyzed theoretically and experimentally.The feasibility of extracting feedback signals from the PADC system was derived.A high-stability channel-interleaved PADC was constructed by extracting a feedback signal from a parallel demultiplexing module to control the MZM-based photonic switch’s driving voltage.Consequently,the amplitude mismatch between the channels was limited to within 0.3 d B over 12 hours of operation.展开更多
This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC） with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog con...This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC） with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter （MDAC） while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18μm CMOS process, occupies an active area of 2.3 × 1.6 mm^2, and consumes 205 mW at 1.8 V.展开更多
Time interleaved analog-to-digital conversion （TIADC） based on parallelism is an effective way to meet the requirement of the ultra-fast waveform digitizer beyond Gsps. Different methods to correct the mismatch erro...Time interleaved analog-to-digital conversion （TIADC） based on parallelism is an effective way to meet the requirement of the ultra-fast waveform digitizer beyond Gsps. Different methods to correct the mismatch errors among different analog-to-digital conversion channels have been developed previously. To overcome the speed limi- tation in hardware design and to implement the mismatch correction algorithm in real time, this paper proposes a fully parallel correction algorithm. A 12-bit l-Gsps waveform digitizer with ENOB around 10.5 bit from 5 MHz to 200 MHz is implemented based on the real-time correction algorithm.展开更多
Based on a 5 MSBs （most-significant-bits）-plus-5 LSBs （least-significant-bits） C-R hybrid D/A conver sion and low-offset pseudo-differential comparison approach, with capacitor array axially symmetric layout topol...Based on a 5 MSBs （most-significant-bits）-plus-5 LSBs （least-significant-bits） C-R hybrid D/A conver sion and low-offset pseudo-differential comparison approach, with capacitor array axially symmetric layout topology and resistor string low gradient mismatch placement method, an 8-channel 10-bit 200-kS/s SAR ADC （successiveapproximation-register analog-to-digital converter） IP core for a touch screen SoC （system-on-chip） is implemented in a 0.18 μm 1P5M CMOS logic process. Design considerations for the touch screen SAR ADC are included. With a 1.8 V power supply, the DNL （differential non-linearity） and INL （integral non-linearity） of this converter are measured to be about 0.32 LSB and 0.81 LSB respectively. With an input frequency of 91 kHz at 200-kS/s sampling rate, the spurious-free dynamic range and effective-number-of-bits are measured to be 63.2 dB and 9.15 bits respectively, and the power is about 136 μW. This converter occupies an area of about 0.08 mm^2. The design results show that it is very suitable for touch screen SoC applications.展开更多
A low power 10-bit 125-MSPS charge-domain(CD) pipelined analog-to-digital converter(ADC) based on MOS bucket-brigade devices(BBDs) is presented.A PVT insensitive boosted charge transfer(BCT) that is able to reject the...A low power 10-bit 125-MSPS charge-domain(CD) pipelined analog-to-digital converter(ADC) based on MOS bucket-brigade devices(BBDs) is presented.A PVT insensitive boosted charge transfer(BCT) that is able to reject the charge error induced by PVT variations is proposed.With the proposed BCT,the common mode charge control circuit can be eliminated in the CD pipelined ADC and the system complexity is reduced remarkably.The prototype ADC based on the proposed BCT is realized in a 0.18μm CMOS process,with power consumption of only 27 mW at 1.8-V supply and active die area of 1.04 mm^2.The prototype ADC achieves a spurious free dynamic range(SFDR) of 67.7 dB,a signal-to-noise ratio(SNDR) of 57.3 dB,and an effective number of bits(ENOB) of 9.0 for a 3.79 MHz input at full sampling rate.The measured differential nonlinearity(DNL) and integral nonlinearity (INL) are +0.5/-0.3 LSB and +0.7/-0.55 LSB,respectively.展开更多
A feed-forward Common-Mode （CM） charge control circuit for a high-speed Charge-Domain （CO） pipelined Analog-to-Digital Converter （ADC） is presented herein. This study aims at solving the problem whereby the prec...A feed-forward Common-Mode （CM） charge control circuit for a high-speed Charge-Domain （CO） pipelined Analog-to-Digital Converter （ADC） is presented herein. This study aims at solving the problem whereby the precision of CD pipelined ADCs is restricted by the variation in input CM charge, which can compensate for CM charge errors caused by a variation in CM charge input in real time. Based on the feed-forward CM charge control circuit, a 12-bit 250-MS/s CD pipelined ADC is designed and realized using a 1P6M 0.18-μm CMOS process. The ADC achieved a Spurious Free Dynamic Range （SFDR） of 78.1 dB and a Signal-to-Noise-and-Distortion Ratio （SNDR） of 64.6 dB for a 20.1-MHz input; a SFDR of 74.9 dB and SNDR of 62.0 dB were achieved for a 239.9-MHz input at full sampling rate. The variation in signal-to-noise ratio was less than 3 dB over a 0-1.2 V input CM voltage range. The power consumption of the prototype ADC is only 85 mW at 1.8 V supply, and it occupies an active die area of 2.24 mm^2.展开更多
We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of pho...We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.展开更多
Asynchronous successive approximation register （SAR） analog-to-digital converters （ADC） feature high energy efficiency but medium performance. From the point of view of speed, the key bottleneck is the unit ca- pa...Asynchronous successive approximation register （SAR） analog-to-digital converters （ADC） feature high energy efficiency but medium performance. From the point of view of speed, the key bottleneck is the unit ca- pacitor size. In this paper, a small size three-dimensional （3-D） metal-oxide-metal （MOM） capacitor is proposed. The unit capacitor has a capacitance of 1-fF. It shapes as an umbrella, which is designed for fast settling consideration. A comparison among the proposed capacitor with other 3-D MOM capacitors is also given in the paper. To demonstrate the effectiveness of the MOM capacitor, a 6-b capacitive DAC is implemented in TSMC 1P9M 65 nm LP CMOS technology. The DAC consumes a power dissipation of 0.16 mW at the rate of 100 MS/s, excluding a source-follower based output buffer. Static measurement result shows that 1NL is less than -4-1 LSB and DNL is less than ＋0.5 LSB. In addition, a 100 MS/s 9-bit SAR ADC with the proposed 3-D capacitor is simulated.展开更多
This paper describes a fast digital calibration scheme for pipelined analog-to-digital converters（ADCs）. The proposed method corrects the nonlinearity caused by finite opamp gain and capacitor mismatch in multiplyin...This paper describes a fast digital calibration scheme for pipelined analog-to-digital converters（ADCs）. The proposed method corrects the nonlinearity caused by finite opamp gain and capacitor mismatch in multiplying digital-to-analog converters（MDACs）.The considered calibration technique takes the advantages of both foreground and background calibration schemes.In this combination calibration algorithm,a novel parallel background calibration with signal-shifted correlation is proposed,and its calibration cycle is very short.The details of this technique are described in the example of a 14-bit 100 Msample/s pipelined ADC.The high convergence speed of this background calibration is achieved by three means.First,a modified 1.5-bit stage is proposed in order to allow the injection of a large pseudo-random dithering without missing code.Second,before correlating the signal,it is shifted according to the input signal so that the correlation error converges quickly.Finally,the front pipeline stages are calibrated simultaneously rather than stage by stage to reduce the calibration tracking constants.Simulation results confirm that the combination calibration has a fast startup process and a short background calibration cycle of 2×2^（21） conversions.展开更多
基金the National Natural Science Foundation of China （60331010, 60271018）.
文摘The electromagnetic radiation will result in informa- tion leakage being recovered when computers work. This article presents a high-speed real-time data acquisition system based on peripheral component interconnect （PCI） bus and field programmable gate array （FPGA） for sampling electromagnetic radiation caused by video signal. The hardware design and controlling flow of each module are introduced in detail. The sampling rate can reach 64 Msps and system transfers speed can be up to 128 Mb/s by using time interleaving, which increases the overall sampling speed of a system by operating two data converters in parallel.
基金supported by the Major National Science & Technology Program of China under Grant No.2012ZX03004004-002National High Technology Research and Development Program of China under Grant No. 2013AA014302
文摘A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.
基金the Natural Science Basic Research Project of Shaanxi Province,China(2020JM-583)。
文摘Addressing the impact of capacitor mismatch on the conversion accuracy of successive approximation register analog-to-digital converter(SAR ADC),a 12-bit 1 MS/s sub-binary SAR ADC designed using variable step size digital calibration was proposed.The least mean square(LMS)calibration algorithm was employed with a ramp signal used as the calibration input.Weight errors,extracted under injected disturbances,underwent iterative training to optimize weight values.To address the trade-off between conversion accuracy and speed caused by a fixed step size,a novel variable step size algorithm tailored for SAR ADC calibration was proposed.The core circuit and layout of the SAR ADC were implemented using the Taiwan Semiconductor Manufacturing Company(TSMC)0.35μm complementary metal-oxide-semiconductor(CMOS)commercial process.Simulation of the SAR ADC calibration algorithm was conducted using Simulink,demonstrating quick convergence and meeting conversion accuracy requirements compared to fixed step size simulation.The results indicated that the convergence speed of the LMS digital calibration algorithm with variable step size was approximately eight times faster than that with a fixed step size,also yielding a lower mean square error(MSE).After calibration,the simulation results for the SAR ADC exhibited an effective number of bit(ENOB)of 11.79 bit and a signal-to-noise and distortion ratio(SNDR)of 72.72 dB,signifying a notable enhancement in the SAR ADC performance.
基金Project supported by the National Natural Science Foundation of China(No.61234003)the Special Funds for Major State Basic Research Project of China(No.2011CB932902)
文摘This paper presents a 12-bit column-parallel successive approximation register analog-to-digital con- verter （SAR ADC） for high-speed CMOS image sensors. A segmented binary-weighted switched capacitor digital- to-analog converter （CDAC） and a staggered structure MOM unit capacitor is used to reduce the ADC area and to make its layout fit double pixel pitches. An electrical field shielding layout method is proposed to eliminate the parasitic capacitance on the top plate of the unit capacitor. A dynamic power control technique is proposed to reduce the power consumption of a single channel during readout. An off-chip foreground digital calibration is adopted to compensate for the nonlinearity due to the mismatch of unit capacitors among the CDAC. The prototype SAR ADC is fabricated in a 0.18 μm 1P5M CIS process. A single SAR ADC occupies 20 × 2020μm2. Sampling at 833 kS/s, the measured differential nonlinearity, integral nonlinearity and effective number of bits of SAR ADC with calibration are 0.9/-1 LSB, 1/-1.1 LSB and 11.24 bits, respectively; the power consumption is only 0.26 mW under a 1.8-W supply and decreases linearly as the frame rate decreases.
文摘This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters （ADC）. The new offset averaging design technique takes full advantage of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging techniques to minimize offset-induced ADC nonlinearities. Circuit analysis allows selection of optimum resistance and capacitance averaging factors to achieve maximum offset reduction in ADC designs. The new averaging method is verified in designing a 4 bit 1 Gs/s flash ADC that is implemented in foundry 0.13 μm CMOS technology.
基金Supported by the National Natural Science Foundation of China (No. 61076026)
文摘A novel Time-Interleaved Analog-to-Digital Converter (TIADC) digital background calibration for the mismatches of offsets, gain errors, and timing skews based on split-ADC is proposed. Firstly, the split-ADC channels in present TIADC architecture are designed to convert input signal at two different channel sampling rates so that redundant channel to facilitate pair permutation is avoided. Secondly, a high-order compensation scheme for correction of timing skew error is employed for effective calibration to preserve high-resolution when input frequency is high. Numerical simulation performed by MATLAB for a 14-bit TIADC based on 7 split-ADC channels shows that Signal-to-Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) of the TIADC achieve 86.2 dBc and 106 dBc respectively after calibration with normalized input frequency near Nyquist frequency.
文摘With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.
基金This work was supported by the National Research Foundation of Korea(NRF)grant funded by theKorea government(MSIT)(No.2022R1A5A8026986)and supported by Institute of Information&communications Technology Planning&Evaluation(IITP)grant funded by the Korea government(MSIT)(No.2020-0-01304,Development of Self-learnable Mobile Recursive Neural Network Processor Technology)+3 种基金It was also supported by the MSIT(Ministry of Science and ICT),Korea,under the Grand Information Technology Research Center support program(IITP-2022-2020-0-01462)supervised by the“IITP(Institute for Information&communications Technology Planning&Evaluation)”supported by the National Research Foundation of Korea(NRF)grant funded by the Korea government(MSIT)(No.2021R1F1A1061314)In addition,this work was conducted during the research year of Chungbuk National University in 2020.
文摘As deep learning techniques such as Convolutional Neural Networks(CNNs)are widely adopted,the complexity of CNNs is rapidly increasing due to the growing demand for CNN accelerator system-on-chip(SoC).Although conventional CNN accelerators can reduce the computational time of learning and inference tasks,they tend to occupy large chip areas due to many multiply-and-accumulate(MAC)operators when implemented in complex digital circuits,incurring excessive power consumption.To overcome these drawbacks,this work implements an analog convolutional filter consisting of an analog multiply-and-accumulate arithmetic circuit along with an analog-to-digital converter(ADC).This paper introduces the architecture of an analog convolutional kernel comprised of low-power ultra-small circuits for neural network accelerator chips.ADC is an essential component of the analog convolutional kernel used to convert the analog convolutional result to digital values to be stored in memory.This work presents the implementation of a highly low-power and area-efficient 12-bit Successive Approximation Register(SAR)ADC.Unlink most other SAR-ADCs with differential structure;the proposed ADC employs a single-ended capacitor array to support the preceding single-ended max-pooling circuit along with minimal power consumption.The SARADCimplementation also introduces a unique circuit that reduces kick-back noise to increase performance.It was implemented in a test chip using a 55 nm CMOS process.It demonstrates that the proposed ADC reduces Kick-back noise by 40%and consequently improves the ADC’s resolution by about 10%while providing a near rail-to-rail dynamic rangewith significantly lower power consumption than conventional ADCs.The ADC test chip shows a chip size of 4600μm^(2)with a power consumption of 6.6μW while providing an signal-to-noise-and-distortion ratio(SNDR)of 68.45 dB,corresponding to an effective number of bits(ENOB)of 11.07 bits.
基金Project supported by the National Natural Science Foundation of China(Nos.60906009,60773025)the Postdoctoral Science Foundation of China(No.20090451423)the National Labs of Analog Integrated Circuits Foundation(No.9140C0901110902)
文摘A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital con- verter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.
基金supported by the National Natural Science Foundation of China(No.60906012)
文摘This paper presents a low-power high-precision switched-opamp（SO）-based delta-sigma（△Σ） analog-to -digital converter（ADC）.The proposed SO design allows circuit operation at sub-1 V supply voltage,only needs to work in half of a clock cycle,and thus is suitable for low power applications.In addition,an opamp-sharing technique is applied to save on hardware overheads.Due to the use of a dual cycle shift data weighted averaging （DCS-DWA） technique,mismatch errors caused in the feedback DAC have been eliminated without introducing signal-dependent tones.The proposed ADC has been implemented in a standard 0.18μm process and measured to have a 92.2 dB peak SNDR and 94.1 dB dynamic range with 25 kHz signal bandwidth.The power consumption is 58μW for the modulator at 0.9 V supply voltage and 96μW for the decimation filter,which translate to the figure-of-merit（FOM） of 35.4 fJ/step for the solo modulator,and 94 fJ/step for the whole system.
基金partially supported by the National Natural Science Foundation of China(Nos.61822508,61571292,and 61535006)
文摘This Letter theoretically and experimentally studies the response of photonic switching in a channel-interleaved photonic analog-to-digital converter(PADC) with high sampling rate and wide input frequency range. A figure of merit(FoM) is introduced to evaluate the switching response of the PADC when a dual-output Mach–Zehnder modulator(MZM) serves as the photonic switch to parallelize the sampled pulse train into two channels. After the optimization of the FoM and utilization of the channel-mismatch compensation algorithm,the system bandwidth of PADC is expanded and the signal-to-distortion ratio is enhanced.
基金This work was partially supported by the National Natural Science Foundation of China(Nos.61571292,61535006,and 61822508).
文摘We investigate a channel-interleaved photonic analog-to-digital conversion(PADC)system’s ability to work stably over a long duration with an optimal driving voltage.The influence of optimum bias point drift of a Mach–Zehnder modulator(MZM)-based photonic switch on this system was analyzed theoretically and experimentally.The feasibility of extracting feedback signals from the PADC system was derived.A high-stability channel-interleaved PADC was constructed by extracting a feedback signal from a parallel demultiplexing module to control the MZM-based photonic switch’s driving voltage.Consequently,the amplitude mismatch between the channels was limited to within 0.3 d B over 12 hours of operation.
文摘This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC） with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter （MDAC） while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18μm CMOS process, occupies an active area of 2.3 × 1.6 mm^2, and consumes 205 mW at 1.8 V.
基金Supported by Knowledge Innovation Program of Chinese Academy of Sciences(KJCX2-YW-N27)National Natural Science Foundation of China(11175176,10476028)
文摘Time interleaved analog-to-digital conversion （TIADC） based on parallelism is an effective way to meet the requirement of the ultra-fast waveform digitizer beyond Gsps. Different methods to correct the mismatch errors among different analog-to-digital conversion channels have been developed previously. To overcome the speed limi- tation in hardware design and to implement the mismatch correction algorithm in real time, this paper proposes a fully parallel correction algorithm. A 12-bit l-Gsps waveform digitizer with ENOB around 10.5 bit from 5 MHz to 200 MHz is implemented based on the real-time correction algorithm.
基金Project supported by the National Natural Science Foundation of China(Nos.60725415,60971066,60676009,60776034,60803038)the National High-Tech Research and Development Program of China(Nos.2009AA01Z258,2009AA01Z260)the National Science & Technology Important Project of China(No.2009ZX01034-002-001-005)
文摘Based on a 5 MSBs （most-significant-bits）-plus-5 LSBs （least-significant-bits） C-R hybrid D/A conver sion and low-offset pseudo-differential comparison approach, with capacitor array axially symmetric layout topology and resistor string low gradient mismatch placement method, an 8-channel 10-bit 200-kS/s SAR ADC （successiveapproximation-register analog-to-digital converter） IP core for a touch screen SoC （system-on-chip） is implemented in a 0.18 μm 1P5M CMOS logic process. Design considerations for the touch screen SAR ADC are included. With a 1.8 V power supply, the DNL （differential non-linearity） and INL （integral non-linearity） of this converter are measured to be about 0.32 LSB and 0.81 LSB respectively. With an input frequency of 91 kHz at 200-kS/s sampling rate, the spurious-free dynamic range and effective-number-of-bits are measured to be 63.2 dB and 9.15 bits respectively, and the power is about 136 μW. This converter occupies an area of about 0.08 mm^2. The design results show that it is very suitable for touch screen SoC applications.
基金supported by the National Natural Science Foundation of China(No.61106027)the 333 Talent Project of Jiangsu Province, China(No.BRA2011115)
文摘A low power 10-bit 125-MSPS charge-domain(CD) pipelined analog-to-digital converter(ADC) based on MOS bucket-brigade devices(BBDs) is presented.A PVT insensitive boosted charge transfer(BCT) that is able to reject the charge error induced by PVT variations is proposed.With the proposed BCT,the common mode charge control circuit can be eliminated in the CD pipelined ADC and the system complexity is reduced remarkably.The prototype ADC based on the proposed BCT is realized in a 0.18μm CMOS process,with power consumption of only 27 mW at 1.8-V supply and active die area of 1.04 mm^2.The prototype ADC achieves a spurious free dynamic range(SFDR) of 67.7 dB,a signal-to-noise ratio(SNDR) of 57.3 dB,and an effective number of bits(ENOB) of 9.0 for a 3.79 MHz input at full sampling rate.The measured differential nonlinearity(DNL) and integral nonlinearity (INL) are +0.5/-0.3 LSB and +0.7/-0.55 LSB,respectively.
基金supported by National Natural Science Foundation of China under grant No.61704161Key Project of Natural Science of Anhui Provincial Department of Education under grant No.KJ2017A396
文摘A feed-forward Common-Mode （CM） charge control circuit for a high-speed Charge-Domain （CO） pipelined Analog-to-Digital Converter （ADC） is presented herein. This study aims at solving the problem whereby the precision of CD pipelined ADCs is restricted by the variation in input CM charge, which can compensate for CM charge errors caused by a variation in CM charge input in real time. Based on the feed-forward CM charge control circuit, a 12-bit 250-MS/s CD pipelined ADC is designed and realized using a 1P6M 0.18-μm CMOS process. The ADC achieved a Spurious Free Dynamic Range （SFDR） of 78.1 dB and a Signal-to-Noise-and-Distortion Ratio （SNDR） of 64.6 dB for a 20.1-MHz input; a SFDR of 74.9 dB and SNDR of 62.0 dB were achieved for a 239.9-MHz input at full sampling rate. The variation in signal-to-noise ratio was less than 3 dB over a 0-1.2 V input CM voltage range. The power consumption of the prototype ADC is only 85 mW at 1.8 V supply, and it occupies an active die area of 2.24 mm^2.
文摘We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.
文摘Asynchronous successive approximation register （SAR） analog-to-digital converters （ADC） feature high energy efficiency but medium performance. From the point of view of speed, the key bottleneck is the unit ca- pacitor size. In this paper, a small size three-dimensional （3-D） metal-oxide-metal （MOM） capacitor is proposed. The unit capacitor has a capacitance of 1-fF. It shapes as an umbrella, which is designed for fast settling consideration. A comparison among the proposed capacitor with other 3-D MOM capacitors is also given in the paper. To demonstrate the effectiveness of the MOM capacitor, a 6-b capacitive DAC is implemented in TSMC 1P9M 65 nm LP CMOS technology. The DAC consumes a power dissipation of 0.16 mW at the rate of 100 MS/s, excluding a source-follower based output buffer. Static measurement result shows that 1NL is less than -4-1 LSB and DNL is less than ＋0.5 LSB. In addition, a 100 MS/s 9-bit SAR ADC with the proposed 3-D capacitor is simulated.
基金supported by the National Key Project,China(No.2008zx010200001)
文摘This paper describes a fast digital calibration scheme for pipelined analog-to-digital converters（ADCs）. The proposed method corrects the nonlinearity caused by finite opamp gain and capacitor mismatch in multiplying digital-to-analog converters（MDACs）.The considered calibration technique takes the advantages of both foreground and background calibration schemes.In this combination calibration algorithm,a novel parallel background calibration with signal-shifted correlation is proposed,and its calibration cycle is very short.The details of this technique are described in the example of a 14-bit 100 Msample/s pipelined ADC.The high convergence speed of this background calibration is achieved by three means.First,a modified 1.5-bit stage is proposed in order to allow the injection of a large pseudo-random dithering without missing code.Second,before correlating the signal,it is shifted according to the input signal so that the correlation error converges quickly.Finally,the front pipeline stages are calibrated simultaneously rather than stage by stage to reduce the calibration tracking constants.Simulation results confirm that the combination calibration has a fast startup process and a short background calibration cycle of 2×2^（21） conversions.
