A new T-shaped tunnel field-effect transistor(TTFET) with gate dielectric spacer(GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics ...A new T-shaped tunnel field-effect transistor(TTFET) with gate dielectric spacer(GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics such as current-voltage relationships, energy band diagrams, band-to-band tunneling(BTBT) rate and the magnitude of the electric field are investigated by using TCAD simulation. It is found that compared with conventional TTFET and TTFET with gate-drain overlap(GDO) structure, GDS-TTFET not only has the minimum ambipolar current but also can suppress the ambipolar current under a more extensive bias range. Furthermore, the analog/RF performances of GDS-TTFET are also investigated in terms of transconductance, gate-source capacitance, gate-drain capacitance, cutoff frequency, and gain bandwidth production. By inserting a low-κ spacer layer between the gate electrode and the gate dielectric, the GDS structure can effectively reduce parasitic capacitances between the gate and the source/drain, which leads to better performance in term of cutoff frequency and gain bandwidth production. Finally, the thickness of the gate dielectric spacer is optimized for better ambipolar current suppression and improved analog/RF performance.展开更多
Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short c...Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short channel effects （SCEs）, leakage currents, device variability and reliability etc. Nowadays, multigate structure has become the promising candidate to overcome these problems. SO1 FinFET is one of the best multigate structures that has gained importance in all electronic design automation （EDA） industries due to its improved short channel effects （SCEs）, because of its more effective gate-controlling capabilities. In this paper, our aim is to ex- plore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length. Electric field modulation is analyzed with spacer length variation and electrostatic performance is evalu- ated in terms of performance parameter like electron mobility, electric field, electric potential, sub-threshold slope （SS）, ON current （Ion）, OFF current （/off） and Ion/loll ratio. The potential benefits of SOl FinFET at drain-to-source voltage, liDS = 0.05 V and VDS = 0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain （Av）, output conductance （go）, trans-conductance （gin）, gate capacitance （Cgg）, and cut-off frequency OCT = gm/2πCgg） with spacer region variations.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61306116 and 61472322)
文摘A new T-shaped tunnel field-effect transistor(TTFET) with gate dielectric spacer(GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics such as current-voltage relationships, energy band diagrams, band-to-band tunneling(BTBT) rate and the magnitude of the electric field are investigated by using TCAD simulation. It is found that compared with conventional TTFET and TTFET with gate-drain overlap(GDO) structure, GDS-TTFET not only has the minimum ambipolar current but also can suppress the ambipolar current under a more extensive bias range. Furthermore, the analog/RF performances of GDS-TTFET are also investigated in terms of transconductance, gate-source capacitance, gate-drain capacitance, cutoff frequency, and gain bandwidth production. By inserting a low-κ spacer layer between the gate electrode and the gate dielectric, the GDS structure can effectively reduce parasitic capacitances between the gate and the source/drain, which leads to better performance in term of cutoff frequency and gain bandwidth production. Finally, the thickness of the gate dielectric spacer is optimized for better ambipolar current suppression and improved analog/RF performance.
文摘Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short channel effects （SCEs）, leakage currents, device variability and reliability etc. Nowadays, multigate structure has become the promising candidate to overcome these problems. SO1 FinFET is one of the best multigate structures that has gained importance in all electronic design automation （EDA） industries due to its improved short channel effects （SCEs）, because of its more effective gate-controlling capabilities. In this paper, our aim is to ex- plore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length. Electric field modulation is analyzed with spacer length variation and electrostatic performance is evalu- ated in terms of performance parameter like electron mobility, electric field, electric potential, sub-threshold slope （SS）, ON current （Ion）, OFF current （/off） and Ion/loll ratio. The potential benefits of SOl FinFET at drain-to-source voltage, liDS = 0.05 V and VDS = 0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain （Av）, output conductance （go）, trans-conductance （gin）, gate capacitance （Cgg）, and cut-off frequency OCT = gm/2πCgg） with spacer region variations.
